Error detection/correction and fault detection/recovery – Pulse or data error handling – Error count or rate
Reexamination Certificate
1999-01-08
2001-03-27
Chung, Phung M. (Department: 2784)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Error count or rate
C714S704000, C714S795000
Reexamination Certificate
active
06209109
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a code synchronization decision circuit of a Viterbi decoder for deciding as to whether or not code synchronization is established in the Viterbi decoder which is employed in a digital transmission system.
2. Description of Related Art
FIG. 5
is a timing chart showing timings of code synchronization decision operation by a conventional code synchronization decision circuit of a Viterbi decoder. As illustrated in
FIG. 5
, the conventional code synchronization decision circuit of the Viterbi decoder counts the number of errors of symbols over a fixed symbol measuring period, and compares the count value with a predetermined error number (called threshold value from now on). As a result, if the count value does not exceed the threshold value, a decision is made that the code synchronization is established, and otherwise a decision is made that the code synchronization is not established. If the code synchronization is not established, the Viterbi decoder cannot decode a convolutional code correctly. Accordingly, when the code synchronization decision circuit decides that the code synchronization is not established, it outputs a signal notifying of that.
Generally, the conventional code synchronization decision circuit continues counting the number of errors for each symbol measuring period by keeping operation of both the error counter and symbol counter for deciding the code synchronization even during a time period in which a re-encoder that re-encodes the decoded output of the Viterbi decoder produces a signal inappropriate for counting the number of errors immediately after the start of operation, or immediately after the detection of a slip signal notifying that the code synchronization is lost.
As documents disclosing a conventional code synchronization decision circuit of the Viterbi decoder, Japanese patent application laid-open Nos. 5-206872/1993 and 6-260945/1994 are known.
The conventional code synchronization decision circuit of the Viterbi decoder with such an arrangement has the following problems. First, it is difficult for transmission line characteristics a user considered to be correctly reflected on settings when the user establishes the threshold value and the number of symbols counted by the symbol counter. Second, rather much power is wasted by the idle operation during the time period in which the inappropriate signal is supplied for the error counter to count the number of errors.
SUMMARY OF THE INVENTION
The present invention is implemented to solve the foregoing problems. It is therefore an object of the present invention to provide a code synchronization decision circuit of the Viterbi decoder capable of not only enabling a user to set the threshold value and the number of symbols correctly and easily, but also reducing its consumption power.
According to a first aspect of the present invention, there is provided a code synchronization decision circuit of a Viterbi decoder comprising: an error counter for counting a number of errors of symbols over a fixed interval; a symbol counter for counting a number of symbols over the fixed interval; a trigger signal generator for producing a trigger signal every time the symbol counter counts up to a number of symbols which is externally set; a comparator for comparing, in response to the trigger signal supplied from the trigger signal generator, the number of errors counted by the error counter with a predetermined number of errors which is externally set, and for producing one of a synchronization signal indicating that code synchronization is established and a slip signal indicating that the code synchronization is not established; and a masking signal generator for generating a masking signal for suspending operation of the error counter and the symbol counter during a time while a code unsuitable as an input for counting the number of errors will be supplied.
Here, the masking signal generator may comprise a counter for carrying out count operation for an interval corresponding to a delay amount of the Viterbi decoder, and output the masking signal for suspending the operation of the error counter and the symbol counter during the count operation of the counter, wherein the interval corresponding to the delay amount of the Viterbi decoder may correspond to the time period in which the code unsuitable as the input for counting the number of errors will be supplied.
The masking signal generator may produce the masking signal for suspending the operation of the error counter and the symbol counter during a time period in which the code unsuitable as the input for counting the number of errors will be supplied, the time period beginning from a time immediately after one of an external reset signal and the slip signal is supplied, the slip signal being supplied from the comparator when the code synchronization is not established.
The masking signal generator may produce the masking signal for suspending the operation of the error counter and the symbol counter at an initial stage of each symbol measuring period of the symbol counter, the initial stage, during which the code unsuitable as the input for counting the number of errors will be supplied, beginning immediately after one of an external reset signal and the trigger signal is supplied, the trigger signal being supplied from the trigger signal generator.
REFERENCES:
patent: 5054035 (1991-10-01), Tarallo et al.
patent: 5671228 (1997-09-01), Nagashima
patent: 6260945 (1994-09-01), None
Hori Michiru
Koyama Masayuki
Chung Phung M.
Leydig , Voit & Mayer, Ltd.
Mitsubishi Denki & Kabushiki Kaisha
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