Viterbi decoder and synchronism controlling method

Details Viterbi decoder and synchronism controlling method Viterbi decoder and synchronism controlling method

2000-11-03

2003-10-21

Chung, Phung M. (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C714S704000

Reexamination Certificate

active

06637003

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to the synchronism control of a viterbi decoder.
BACKGROUND OF THE INVENTION
In recent years, data transmission by satellite communications and cable has been digitized. In such digitized data transmission, a punctured code is used to realize high-speed data transmission with high error correction capability in a limited frequency band.
On the transmitting side, in compliance with a fixed pattern from a code group of a multiplex code created at a coding rate 1/2, the code is deleted to create a punctured code at a coding rate of n/m (n<m), which is modulated by a digital modulator and transmitted to the receiving side.
On the receiving side, a signal which has been demodulated by a demodulator is error-corrected using a viterbi decoder and output.
The viterbi decoder corrects errors in the demodulated signal by inserting a dummy symbol into the signal output from the demodulator.
The viterbi decoder monitors the number of bits corrected by counting the number of bit errors corrected in a fixed period.
When the insertion position of the dummy symbol is incorrect, i.e. when there is asynchronism, the value of the bit error constant which is monitored by the viterbi decoder becomes large. On the other hand, when the insertion position of the dummy symbol is correct, i.e. when there is synchronism, the value of the bit error constant decreases.
The viterbi decoder determines whether there is asynchronism or synchronism by comparing the number of bit error corrections with a predetermined threshold.
The number of positions where the dummy symbols are inserted is determined based on the coding rate. The viterbi decoder searches for synchronism by shifting the positions in each measurement period and comparing the number of bit error corrections in each aspect with the threshold.
FIG. 12
shows a sequence for creating a punctured code having a coding rate of 3/4 used in QPSK, and
FIG. 11
is a block diagram of a conventional viterbi decoder.
As shown in
FIG. 12
, the punctured code is created by a multiplex coder having a coding rate of 1/2 and a symbol selector.
When a one-bit information group, . . . , i
0
, i
1
, i
2
, . . . has been input into the multiplex coder, the multiplex coder outputs a two-bit coded group, . . . , (X
11
, Y
11
), (X
12
, Y
12
), (X
13
, Y
13
) . . .
The symbol selector outputs (X
11
, Y
11
), (X
12
, Y
12
), (X
13
, Y
13
) as one block after deleting the codes at predetermined positions.
FIG. 12
shows an example where the deleted pattern is (
101
,
110
). As a consequence, (X
11
, Y
11
), (X
12
, Y
12
), (X
13
, Y
13
) becomes (X
11
, Y
11
), (Y
13
, X
12
), and this is output from the symbol selector to the modulator.
The conventional viterbi decoder comprises, as shown in
FIG. 11
, a phase rotator
1
, a dummy symbol inserter
2
, a viterbi decoding section
3
, a multiplex coder
4
, a delay circuit
5
, a synchronism detector
6
, and a measurement period counter
7
.
The synchronism detector
6
outputs a phase changing signal CHPH to the phase rotator
1
, and outputs a dummy symbol position changing signal CHPOS to the dummy symbol inserter
2
.
These two signals adjust the positions at which the dummy symbols are to be inserted into the modulation signal.
The operation of each block of the viterbi decoder will be explained here.
The phase rotator
1
controls (I′, Q′)=(I, Q) when the phase changing signal CHPH is “0”, and controls (I′, Q′)=(Q, −I) when the phase change signal CHPH is “1”.
The dummy symbol inserter
2
changes the insertion position of the dummy symbol when the dummy symbol position changing signal CHPOS has charged.
As an example,
FIG. 13A
to
FIG. 13D
show the output of the dummy symbol inserter
2
when a punctured code at a coding rate of 3/4 has been transmitted.
When coding has-been carried out as explained above, the state in
FIG. 13A
is synchronized, but the states of
FIG. 13B
to
FIG. 13D
are asynchronized.
The viterbi decoding section
3
corrects errors in compliance with a viterbi algorithm based on the signal which is output from the dummy symbol inserter
2
. The multiplex coder
4
codes the corrected output of the viterbi decoding section
3
.
The delay circuit
5
delays the output of the dummy symbol inserter
2
by time T. This delay T is equal to the sum of the delay of the viterbi -decoding section
3
and the delay of the multiplex coder
4
. When the output I and Q (omitted from the figure) of the demodulating section is an n-bit soft determining signal, the delay circuit
5
delays the MSB of I′ and Q′.
The synchronism detector
6
compares the output of the delay circuit
5
with the output of the multiplex coder
4
and counts the number of bit error corrections. The synchronism detector
6
compares this number with an externally set threshold and determines whether the outputs are synchronized or asynchronized. That is, the synchronism detector
6
determines whether the dummy symbols have been inserted at the correct positions.
For example, for a demodulated signal at a coding rate of 3/4, the phase rotator
1
outputs (I′, Q′)=(I, Q), and the output of the dummy symbol inserting circuit is as shown in FIG.
13
B. Therefore, synchronism is controlled in the following way when the viterbi decoder starts correcting errors.
1. First Measurement Period
The viterbi decoded result is determined as asynchronized when the output of the dummy symbol inserter
2
is in the state shown in FIG.
13
B.
Synchronism is achieved by using the phase rotator
1
to control of (I′, Q′)=(I, −Q), or by changing the insertion position of the dummy symbol in the dummy symbol inserter
2
.
When the insertion position of the dummy symbol has been changed, the input into the viterbi decoding section
3
changes from the states shown in
FIG. 13B
to that shown in FIG.
13
D.
2. Second Measurement Period
The viterbi decoded result is determined as asynchronized when the output of the dummy symbol inserter
2
is in the state shown in FIG.
13
B.
The dummy symbol inserter
2
controls of (I′, Q′)=(Q, −I). The input into the viterbi decoding section
3
changes from the state shown in
FIG. 13B
to that of FIG.
13
C.
3. Third Measurement Period
The viterbi decoded result is determined as asynchronized when the output of the dummy symbol inserter
2
is in the state shown in FIG.
13
C.
The phase rotator
1
maintains (I′, Q′)=(Q, −I) while the dummy symbol inserter
2
changes the insertion position of the dummy symbol. The input to the viterbi decoding section
3
changes from that shown in
FIG. 13C
to the one shown in FIG.
13
A.
4. Fourth Measurement Period
When the output of the dummy symbol inserter
2
is in the state shown in
FIG. 13A
, the viterbi decoded result is determined as synchronized.
Viterbi decoding is performed while maintaining the states of the phase rotator
1
and the dummy symbol inserter
2
.
When asynchronism is detected, the phase rotator
1
controls of (I′, Q′)=(I, Q) and the dummy symbol inserter
2
is returned to its-initial state prior to searching for synchronism.
The measurement period counter
7
controls the timing according to which the synchronism detector
6
compares the number of corrected bit errors with the threshold. The measurement period counter
7
is set externally.
In the synchronized state, a synchronism detecting signal is output to the synchronism detector
6
in each measurement period.
In the asynchronized state, a delay T is needed from the point where the output of the dummy symbol inserter
2
changes until a signal is input into the viterbi decoding section
3
and recorded.
In the asynchronized state, the measurement period counter
7
stops the time count during the period T from the change of the output of the dummy symbol inserter
2
, and the synchronism detector
6
stops counting the number of bit error corrections.
When the codi

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