4. Error detection/correction and fault detection/recovery
  5. Pulse or data error handling
  6. Digital logic testing

Michael J. Nesheiwat

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Circuit and method for merging refresh and access operations...

Static information storage and retrieval – Read/write circuit – Data refresh
Reexamination Certificate

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Circuit and system for DRAM refresh with scoreboard methodology

Static information storage and retrieval – Read/write circuit – Data refresh
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Hierarchical directories for cache coherency in a...

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Hierarchical virtual model of a cache hierarchy in a...

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Mechanism for estimating and controlling di/dt-induced power...

Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system – Power system
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Profile ID: LFUS-PAI-P-2481173

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