Marvin W. Martinez, Jr.

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Coherency for write-back cache in a system designed for write-th

Patent

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CPU-peripheral bus interface using byte enable signaling to cont

Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation
Patent

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Generating test input for a circuit

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate

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I/O bus interface recovery counter dependent upon minimum bus cl

Patent

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Method and system for providing clock signals

Pulse or digital communications – Synchronizers
Reexamination Certificate

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Profile ID: LFUS-PAI-P-615965

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