Method and system for providing clock signals

Pulse or digital communications – Synchronizers

Reexamination Certificate

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Details

C370S503000

Reexamination Certificate

active

07116740

ABSTRACT:
Providing clock signals includes receiving a first clock signal at a first clock circuit and at a second clock circuit, where the first clock signal comprises first cycles. A second clock signal is generated from the first clock signal at the first clock circuit, where the second clock signal comprises second cycles and a first cycle corresponds to a first multiple of the second cycles. A third clock signal is generated from the first clock signal at the second clock circuit, where the third clock signal comprises third cycles and a second cycle corresponds to a second multiple of the third cycles. The first clock signal and the second clock signal are sampled using the third clock signal. A safe cycle is determined in response to the sampled clock signals. Data is transferred in accordance with the safe cycle.

REFERENCES:
patent: 5087829 (1992-02-01), Ishibashi et al.
patent: 5734301 (1998-03-01), Lee et al.
patent: 6067335 (2000-05-01), Yamanoi et al.
patent: 6104667 (2000-08-01), Akaogi
patent: 6112308 (2000-08-01), Self et al.
patent: 6127864 (2000-10-01), Mavis et al.
patent: 6182236 (2001-01-01), Culley et al.
patent: 6370200 (2002-04-01), Takahashi

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