Patent
1996-02-13
1999-04-27
Lee, Thomas G.
395880, 395878, G06F 13372
Patent
active
058988157
ABSTRACT:
A bus interface unit of a processor comprises an I/O recovery counter for preventing peripheral overrun due to successive I/O bus cycles. The I/O recovery counter counts the necessary I/O recovery period between I/O bus cycles necessary to prevent peripheral overrun. The I/O recovery counter comprises a clock input from the processor and a signal derived from the bus control signal READY. The I/O recovery counter begins to count at the receipt of the READY signal after the initiation of an I/O bus cycle. The bus interface unit waits until the I/O recovery counter completes its count of the I/O recovery period prior to initiating another I/O bus cycle.
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Bluhm Mark W.
Martinez, Jr. Marvin W.
Lee Thomas G.
Maxin John L.
National Semiconductor Corporation
Yuan Chien
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