4. Electronic digital logic circuitry
  5. Interface
  6. Current driving

Juergen Pianka

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Clock and data recovery with a feedback loop to adjust the...

Coded data generation or conversion – Digital code to digital code converters – To or from nrz codes
Reexamination Certificate

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ESD protection of output buffers

Electricity: electrical systems and devices – Safety and protection of systems and devices – Load shunting by fault responsive means
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ESD protection of output buffers

Electricity: electrical systems and devices – Safety and protection of systems and devices – Load shunting by fault responsive means
Patent

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High speed CMOS output buffer using 3 volt or lower supply volta

Electronic digital logic circuitry – Interface – Current driving
Patent

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Variable phase shifting clock generator

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Clock or pulse waveform generating
Reexamination Certificate

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Profile ID: LFUS-PAI-P-181389

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