High speed CMOS output buffer using 3 volt or lower supply volta

Details High speed CMOS output buffer using 3 volt or lower supply volta High speed CMOS output buffer using 3 volt or lower supply volta

1996-12-03

1998-10-06

Westin, Edward P.

Electronic digital logic circuitry

Interface

Current driving

326 27, H03K 190175, H03K 1716

Patent

active

058182624

ABSTRACT:
A integrated circuit buffer includes a first inverter comprising a pull-up transistor of a first conductivity type (e.g., p-channel) and a pull-down transistor of a second conductivity type (e.g., n-channel) for driving a load. The buffer further includes a second inverter comprising a pull-up transistor of the second conductivity type (e.g., n-channel) and a pull-down transistor of the first conductivity type (e.g., p-channel) that also drives the load. The first and second inverters are driven by a drive circuit that provides signals that are substantially out of phase. Therefore, in operation the pull-up transistors are active during a first time period, and the pull-down transistors are active during a second time period. In this manner, the drive capability of the buffer is improved in the face of voltage bounce on the power supply bondpads, which is typically due to package inductance. In a preferred embodiment, the power supply voltages to the first and second inverters are provided through bondpads that are separate from those that provide the power supply voltages to the drive circuitry, thereby providing relatively low noise power to the drive circuitry.

REFERENCES:
patent: 5065224 (1991-11-01), Fraser et al.
patent: 5192879 (1993-03-01), Aoki
patent: 5204554 (1993-04-01), Ohannes
patent: 5206544 (1993-04-01), Chen
patent: 5256916 (1993-10-01), Thurston
patent: 5319260 (1994-06-01), Wanless
patent: 5332932 (1994-07-01), Runaldue
patent: 5604453 (1997-02-01), Pedersen
Carver Mead, Introduction to VLSI Systems, 1980, pp. 33-37.

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