ESD protection of output buffers

Electricity: electrical systems and devices – Safety and protection of systems and devices – Load shunting by fault responsive means

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361 91, 361111, 361118, H02H 904

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active

053453565

ABSTRACT:
A particular electrostatic discharge (ESD) protection problem is faced when only n-channel output transistors are present, since there is no p-n junction that could serve to clamp positive ESD voltages, as would be the case if a p-channel output transistor were present. In the present technique, the output transistor itself is used to conduct the ESD current to a power supply conductor (V.sub.SS). To assist in the turn-on of the n-channel output transistor, a transistor couples the bond pad to the n-tub in which the p-channel pre-driver transistor is formed. Conduction through this transistor raises the n-tub voltage when an ESD event occurs, thereby preventing the p-n junction of the p-channel pre-driver transistor from clamping the turn-on voltage, which would limit the protection obtained by this technique. This technique is especially valuable for SCSI (Small Computer System Interface) chips, since only n-channel output transistors are used. It may also be used in TTL-output buffers, which also use n-channel pull-up and pull-down devices. P-channel devices may be comparably protected.

REFERENCES:
patent: 4806999 (1989-02-01), Strauss
patent: 4990802 (1991-02-01), Smooha
patent: 5208719 (1993-05-01), Wei
"Dynamic Gate Coupling of NMOS For Efficient Output ESD Protection", by Charvaka Duvvury and Carlos Diaz, Texas Instruments Inc., Semiconductor Process Design Center, pp. 141 through 150, 30th Annual Proceedings, Reliability Physics 1992, San Diego, Calif., Mar. 31, Apr. 1, 2, 1992.
IEEE Catalog No. 92CH3084-1, Sponsored by the IEEE Electron Devices Society and the IEEE Reliability Society, Copy 1992 by the Institute of Electrical and Electronics Engineers, Inc., 345 E. 47th St., New York, NY 10017.

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