Coded data generation or conversion – Digital code to digital code converters – To or from nrz codes
Reexamination Certificate
2002-04-10
2004-05-18
Young, Brian (Department: 2819)
Coded data generation or conversion
Digital code to digital code converters
To or from nrz codes
C375S317000, C375S374000, C375S375000, C375S376000
Reexamination Certificate
active
06737995
ABSTRACT:
BACKGROUND
This disclosure relates to clock and data recovery techniques.
Receivers in communications systems may perform various functions including receiving data signals and recovering timing signals from the received data signals. In some communications systems, the incoming data signals are transmitted using a non-return to zero (NRZ) format. A nonlinear circuit may be used to detect timing information and to recover the clock signal from the NRZ format data stream.
Direct current (DC) offsets may be introduced into the data recovery process as a result of analog processing circuitry such as amplifiers, filters and flip-flops. The DC offset associated with such circuitry may result in a signal level shift which, if left uncorrected, can degrade performance of the data recovery system.
SUMMARY
In general, techniques are disclosed that may aid in the recovery of clock and data signals.
In one implementation, an apparatus includes an input to receive a stream of incoming data signals. A timing acquisition circuit including a sampling circuit to sample the incoming data signals. The timing acquisition circuit extracts clock information from the incoming data signals and provides re-timed signals corresponding to the incoming data signals based on the extracted clock information. A feedback loop coupled between an output of the timing acquisition circuit and the input adjusts a slice level of the sampling circuit based on a transition bit sampled from the stream.
According to one aspect, a method includes receiving a stream of incoming data signals and determining an offset based, at least in part, on the state of a transition bit sampled from the stream of incoming data signals. The slice level of an input sampling circuit is adjusted based on the offset. The method includes generating re-timed data signals corresponding to the incoming data signals.
According to another aspect, a method includes receiving a stream of incoming data signals and generating re-timed data bits corresponding to the incoming data signals. An offset cancellation signal is provided to cancel amplitude offset from signals in the stream. The method includes adjusting the offset cancellation signal based on a state of a transition bit occurring between re-timed data bits.
In various implementations, one or more of the following features may be present. Determining an offset may include examining a pair of consecutive data bits and an intervening transition bit. A signal corresponding to a detected offset may be provided based on the examined data bits and transition bit. The techniques may include repeatedly examining subsequent groups of consecutive data bits and an intervening transition bit and providing signals indicative of the detected offsets. In some cases, the techniques include averaging or integrating the signals corresponding to the detected offsets.
The techniques may be applied to a stream of incoming data signals in a non-return to zero format, as well as to data streams in other formats.
In some implementations, the timing acquisition circuit may include a phase detector. The apparatus may include a phase locked loop circuit that may include the phase detector. The timing acquisition circuit may be configured to sample data and transition bits from the incoming stream based on a timing signal from the phase locked loop.
The circuitry to adjust the slice level may be implemented in various ways. For example, the circuitry may include a charge pump, as well as a loop filter coupled to an output of the charge pump. Alternatively, the circuitry may include a continuous-time low-pass filter. In other implementations, the circuitry may include a digital low-pass filter, as well as a digital-to-analog converter coupled to an output of the low-pass filter.
The circuitry to adjust the slice level may be configured to provide signals indicative of how to adjust the slice level based on respective states of transition bits occurring between pairs of re-timed data bits. In some implementations, the circuitry includes a counter to integrate the signals indicative of how to adjust the slice level. The counters may generate a signal indicating that the slice level should be adjusted, for example, if one of the counters reaches a predetermined count. The circuitry also may be configured to keep track of the number of times that data bits and an intervening transition bit have the same value and to adjust the slice level if the data and transition bits have the same value consecutively for a predetermined number of times.
Various implementations may include one or more of the following advantages. The same circuit may be used to perform the timing recovery process and offset measurement, thereby reducing the overall number of components required. The techniques may reduce or eliminate residual sources of DC offset, including offset from front-end circuitry as well as offset from the phase detector and sampling flip-flops. Furthermore, the techniques need not be constrained by the assumption inherent in some clock and data recovery systems that the density of logical “1”s and “0”s in the pattern of data bits in the data stream is substantially equal. The techniques may provide increased sensitivity of detection and reduced jitter in the timing recovery process.
Other features and advantages will be readily apparent from the following detailed description, the accompanying drawings and the claims.
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Khoury, Jr. John Michael
Miao Guoqing
Ng Devin Kenji
Pianka Juergen
Fish & Richardson P.C.
Nguyen John
Young Brian
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