Variable phase shifting clock generator

Details Variable phase shifting clock generator Variable phase shifting clock generator

1999-06-28

2001-07-10

Tran, Toan (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Clock or pulse waveform generating

C327S269000, C327S149000

Reexamination Certificate

active

06259295

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to the generation of periodic waveforms and, more particularly, to a clock phase generator which can generate a plurality of sub-clock phases in between the standard clock phases.
BACKGROUND OF THE INVENTION
For many analog and digital applications, it is necessary to generate clock signals which have well defined, known clock phases. Such applications include data and clock recovery circuits, data acquisition systems, pulse wave modulation generators and clock multipliers.
FIG. 1
illustrates a typical clock signal C
1
having a period P. A phase delay D can be introduced by delaying the clock by a time period of D (e.g., two nanoseconds) and outputting the delayed clock signal as a second clock output C
2
.
Thus, for example, if clock signal C
1
has a period P of 8 nanoseconds, then by introducing a two nanosecond delay D to each successive clock signal, four clock signals, C
1
through C
4
, can be utilized for control purposes, all generated based on the first clock signal C
1
.
Using prior art techniques, evenly spaced clock signals are generated with multi-phase clock generators and delay-locked loops (DLLs). U.S. Pat. No. 5,436,939 to Co et al., incorporated herein by reference, teaches one such multi-phase clock generator. Both multi-phase clock generators and DLLs use a series of delay elements to generate a plurality of output clock signals from “taps”; the phase delay D associated with a particular tap is referred to as a “tap delay.” Using these prior art schemes, the size of the tap delay is limited by the speed of the intrinsic delay of the delay cell plus the delay from the load the delay cell drives. For example, it is common to utilize a series of inverters in a voltage controlled oscillator (VCO) to implement the phase delay D; however, the smallest possible delay using state-of-the-art inverters is ∝200 pS. Thus, for example, across an 8 nanosecond (8000 pS) period, the maximum number of taps that could be available would be 40 (8000 pS÷200 pS=40). Therefore, conventional multi-phase clock generators and DLLs are not suitable for applications requiring tap delays that are smaller than the intrinsic delay of the delay cell. Further, conventional multi-phase clock generators and DLLs are unsuitable for applications requiring variable phase shifting clock signals, since they cannot output clock signals that have a variable phase delay.
Accordingly, there exists a need for a multi-phase clock generator which can produce a variable phase shifting clock signal with tap delays that are less than the intrinsic delay of conventional delay cells.
SUMMARY OF THE INVENTION
According to the present invention, the minimum and maximum delay values achievable by a standard multi-phase clock generator or DLL are determined to establish a range of potential delays of the clock generator, and then sub-taps or “virtual taps” are embedded within the delay range to enable smaller delays to be selected and added to the output clock signal from each tap.


REFERENCES:
patent: 4626911 (1986-12-01), Sasaki et al.
patent: 5107264 (1992-04-01), Novof
patent: 5436939 (1995-07-01), Co et al.
patent: 5633608 (1997-05-01), Danger
patent: 5689530 (1997-11-01), Honaker, Jr.
patent: 5786732 (1998-07-01), Nielson
patent: 5815041 (1998-09-01), Lee et al.
patent: 5838204 (1998-11-01), Yao
patent: 5838205 (1998-11-01), Ferraiolo et al.
patent: 5864250 (1999-01-01), Deng
patent: 6005447 (1999-12-01), Huang

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