4. Error detection/correction and fault detection/recovery
  5. Data processing system error or fault handling
  6. Reliability and availability

Jude A. Rivers

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Cost-conscious pre-emptive cache line displacement and...

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Distributed buffer integrated cache memory organization and...

Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
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Extending the number of instruction bits in processors with...

Electrical computers and digital processing systems: processing – Instruction decoding – Decoding instruction to accommodate variable length...
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Extending the number of instruction bits in processors with...

Electrical computers and digital processing systems: processing – Instruction decoding – Decoding instruction to accommodate variable length...
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Method and apparatus for an efficient multi-path trace cache...

Electrical computers and digital processing systems: processing – Instruction fetching
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Profile ID: LFUS-PAI-P-2246457

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