Cost-conscious pre-emptive cache line displacement and...

Details Cost-conscious pre-emptive cache line displacement and... Cost-conscious pre-emptive cache line displacement and...

2005-01-13

2008-11-18

Ellis, Kevin (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S134000, C711S136000, C711S159000, C711S160000

Reexamination Certificate

active

07454573

ABSTRACT:
A hardware based method for determining when to migrate cache lines to the cache bank closest to the requesting processor to avoid remote access penalty for future requests. In a preferred embodiment, decay counters are enhanced and used in determining the cost of retaining a line as opposed to replacing it while not losing the data. In one embodiment, a minimization of off-chip communication is sought; this may be particularly useful in a CMP environment.

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Tanenbaum, Andrew. Structured Computer Organization. 194. Prentice Hall, Inc. pp. 10-12.
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Lenoski and Weber, Scalable Shared Memory Multi-Processing, Section 1.2.2, pp. 16-20, Morgan-Kaufman, 1995

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