Extending the number of instruction bits in processors with...

Electrical computers and digital processing systems: processing – Instruction decoding – Decoding instruction to accommodate variable length...

Reexamination Certificate

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Details

C712S209000, C712S300000, C712S233000, C711S123000, C714S053000

Reexamination Certificate

active

07340588

ABSTRACT:
This invention pertains to apparatus, method and a computer program stored on a computer readable medium. The computer program includes instructions for use with an instruction unit having a code page, and has computer program code for partitioning the code page into at least two sections for storing in a first section thereof a plurality of instruction words and, in association with at least one instruction word, for storing in a second section thereof an extension to each instruction word in the first section. The computer program further includes computer program code for setting a state of at least one page table entry bit for indicating, on a code page by code page basis, whether the code page is partitioned into the first and second sections for storing instruction words and their extensions, or whether the code page is comprised instead of a single section storing only instruction words.

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The Run-time Architecture Team, The 32-bit PA-RISC Run-time Architecture Document, 1997.
Motorola, MCF5249 Integrated ColdFire Microprocessor Product Brief, 2002.
“Demystifying EPIC and IA-64, EPIC Is a Natural Evolution of RISC, Making It Easy to Retrofit Onto RISC”, Peter Song, Microdesign Resources, Jan. 26, 1998, 7 pages.

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