Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2000-11-02
2004-06-08
Chung, Phung M. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S724000
Reexamination Certificate
active
06748563
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates generally to boundary scan testing in integrated circuits, and more particularly, to boundary scan dynamic testing in an integrated circuit having pipelined clock distribution.
2. Description of the Related Art
Functional testing of integrated circuits and printed circuit boards is necessary to assure defect-free products. Using a low pin-count serial interface, the Joint Test Action Group (JTAG) interface provides a mechanism for testing both the internal features of an integrated circuit and the connections between two integrated circuits mounted on a printed circuit board or other substrate. The details of the JTAG interface are defined by IEEE (Institute of Electrical and Electronics Engineers) standard 1149.1—IEEE Standard Test Access Port and Boundary Scan Architecture.
Present implementations of boundary scan circuits require special control of the boundary scan latch clock signals. The boundary scan latches are typically implemented in pairs, with one latch a master for holding scan data and one latch a slave for maintaining the scan data as it is clocked into an adjacent block. The blocks are serially connected in scan chains, permitting values to be shifted in and out of the blocks without a parallel signal connection.
In integrated circuits such as microprocessors that normally operate at high frequencies, dynamic tests, commonly referred to as “A/C tests” can be performed by ensuring that the tester clock used during the test is at a frequency low enough for functional logic path delays to be overcome by the time the test results are sampled. These tests may test functional logic, such as bus interface connections, that run at a slower clock frequency than the microprocessor system clock. The clocks in these portions of the logic are commonly clocked at a clock frequency produced by dividing the system clock via an N:1 divider that may be programmable.
However, in clocking schemes such as the pipelined clock architecture disclosed in “METHOD AND APPARATUS FOR SCANNING AND CLOCKING CHIPS WITH A HIGH-SPEED FREE RUNNING CLOCK IN A MANUFACTURING TEST ENVIRONMENT,” the use of pipelined control signals introduces pipeline delays and prevent the possibility of setting functional logic values and receiving correct test results from logic having path delays longer than a mesh clock cycle.
In light of the foregoing, it would be desirable to provide a method and apparatus for testing path delays in an integrated circuit having a high-speed boundary scan implementation.
SUMMARY OF THE INVENTION
The objective of performing path delay tests in an integrated circuit having a high-speed boundary scan implementation is accomplished in a method and apparatus for testing path delays. The edge of a tester clock is detected and a clock generating circuit produces a waveform for clocking functional logic within the integrated circuit, where the internal clock is started in response to detection of the edge of the tester clock.
The above as well as additional objectives, features, and advantages of the present invention will become apparent in the following detailed written description.
REFERENCES:
patent: 5740410 (1998-04-01), McDermott
patent: 6091261 (2000-07-01), De Lange
patent: 6151682 (2000-11-01), Van Der Wal et al.
patent: 6219813 (2001-04-01), Bishop et al.
LeBlanc Johnny James
Skergan Timothy
Bracewell & Patterson L.L.P.
Chung Phung M.
International Business Machines - Corporation
Salys Casimer K.
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