Analyzing CMOS circuit delay

Details Analyzing CMOS circuit delay Analyzing CMOS circuit delay

1999-03-25

2002-05-14

Smith, Matthew (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

06389577

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to circuit design methodology and more particularly to a methodology and implementation for designing integrated circuits.
BACKGROUND OF THE INVENTION
Integrated circuits (ICs) or “chips” are the key components in almost all electronic devices and computer systems on the market. As the state-of-the-art in the design and manufacture of such chips continues to advance, the complexity of the chip-design function is becoming more complex and time consuming. As transistor size decreases, larger levels of integration are possible and more functionality can be built into smaller ICs which take up less space in hardware systems.
The design effort of current state-of-the-art microprocessor chips, for example, has grown exponentially with the complexity of the chips. A current typical design may represent tens of millions of transistors. For these designs to be market competitive, they must also achieve the highest possible clock rate to achieve competitive system operating speeds. Clock speeds of 300 MHz today are not uncommon and the clock rates will continue to increase with improvements in integrated circuit design and manufacturing technologies. The higher clock rates are the product of considerable design manpower and designer skill levels for a given CMOS semiconductor process feature size. A clock rate is the frequency or cycle time that every one of tens of millions of possible circuit logic paths must be fast enough to meet. Any one of these millions of paths can become the limiting factor in the upper clock rate limit, which, in turn, will limit the maximum achievable clock rate for the system and also limit the market value of the entire system design.
In designing integrated circuits, it is essential to find the slowest paths within the integrated circuit, and to modify the design or path to make the path faster, i.e. to reduce the time taken between the receipt of an input to the path and the appearance of a resulting output generated in response to the input. As one circuit path speed is increased, it is no longer the slowest path in the system and efforts are focussed on the next or current “slow path” in the circuit. This iterative process continues until the results are optimized relative to other circuit design criteria. In prior art design techniques, “slow paths” frequently escaped detection and identification and avoided optimization resulting in an inefficient circuit design.
In order to “time out” or measure the timing of circuit paths in new chip designs, the delay of each circuit used in the path must be computed. The method used was to create a delay relationship for the circuit where the delay would vary depending upon how the circuit was used or applied in the particular path being analyzed. This was a commonly used method and was used in order to save manpower since a specific circuit type is used many times on a chip design. Each time the circuit is used, the delay relationship is used to determine a new delay for the circuit depending on certain usage parameters such as “input rise time” and “output loading”. Determining the delay relationships within the IC design is quite a sophisticated and complex task and typically requires a massive manpower effort.
Thus, there is a need for an improved methodology and implementing system which is effective to provide improved circuit delay and timing analysis in the design of integrated circuits.
SUMMARY OF THE INVENTION
A method and implementing system is provided in which input specifications, device delays and output loads, for each element in a circuit design, are utilized in an iterative processing engine to objectively determine and provide a timing rule database for a circuit being designed.


REFERENCES:
patent: 5689432 (1997-11-01), Blaauw et al.
patent: 5903475 (1999-05-01), Gupte et al.
patent: 6099581 (2000-08-01), Sakai

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