Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent
1995-10-02
2000-04-25
Beausoliel, Jr., Robert W.
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
G01R 3128
Patent
active
060556587
ABSTRACT:
A system for testing a high speed integrated circuit includes a test device having a test clock with a first maximum frequency for performing level sensitive scan design (LSSD) testing of the integrated circuit device under test, a frequency multiplier circuit for multiplying the test clock signal to a higher second frequency capable of operating the device under test, and a finite state machine for generating a first internal clock for testing the device under test. In a practical embodiment, the internal clock speed may be running at a frequency many multiples of the test clock. Alternatively, a method of testing a device under test (DUT) at design speed includes running a predetermined group of tests with a test device operating at a lower speed than the design speed; incorporating LSSD or boundary scan test techniques in the device under test, together with a frequency multiplying device; generating a global clock for the device under test from the frequency multiplying circuit and using a finite state machine as a synchronizer and pulse generator to control a capture clock with respect to the global clock.
REFERENCES:
patent: 4710927 (1987-12-01), Miller
patent: 4969148 (1990-11-01), Nadeau-Dostie et al.
patent: 5095262 (1992-03-01), Henley et al.
patent: 5181191 (1993-01-01), Farwell
patent: 5208838 (1993-05-01), Wendell et al.
patent: 5254942 (1993-10-01), D'Souza et al.
patent: 5329533 (1994-07-01), Lin
patent: 5355369 (1994-10-01), Greenbergerl et al.
patent: 5381420 (1995-01-01), Henry
patent: 5396170 (1995-03-01), D'Souza et al.
patent: 5453993 (1995-09-01), Kitaguchi et al.
patent: 5524035 (1996-06-01), Casal et al.
patent: 5524114 (1996-06-01), Peng
"Off-Chip Module Clock Controller," IBM Technical Disclosure Bulletin, vol. 32, No. 4A, pp. 77-78, Sep. 1989.
"LOCST: A Built-in Self-test Technique," IEEE Design & Test, pp. 45-52, Nov. 1984.
Jaber Talal Kamel
LeBlanc Johnny James
Walther Ronald Gene
Beausoliel, Jr. Robert W.
England Anthony V. S.
International Business Machines - Corporation
Iqbal Nadeem
Van Leeuwen Leslie A.
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