Borderless vias without degradation of HSQ gap fill layers

Details Borderless vias without degradation of HSQ gap fill layers Borderless vias without degradation of HSQ gap fill layers

1998-05-08

2001-01-30

Everhart, Caridad (Department: 2825)

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

C438S780000, C438S624000

Reexamination Certificate

active

06180534

ABSTRACT:

TECHNICAL FIELD
The present invention relates to high density, multi-metal layer semiconductor device with reliable interconnection patterns. The invention has particular applicability in manufacturing ultra large scale integration multi-metal layer semiconductor devices with design features of 0.25 microns and under.
BACKGROUND ART
The escalating demands for high densification and performance associated with ultra large scale integration semiconductor devices require design features of 0.25 microns and under, such as 0.18 microns, increased transistor and circuit speeds, high reliability and increased manufacturing throughput. The reduction of design features to 0.25 microns and under challenges the limitations of conventional interconnection technology, including conventional photolithographic, etching and deposition techniques.
Conventional methodology for forming patterned metal layers comprises a subtractive etching or etch back step as the primary metal patterning technique. Such a method involves the formation of a first dielectric layer on a semiconductor substrate, typically doped monocrystalline silicon, with conductive contacts formed therein for electrical connection with an active region on the semiconductor substrate, such as a source/drain region. A metal layer, such as aluminum or an aluminum alloy, is deposited on the first dielectric layer, and a photoresist mask is formed on the metal layer having a pattern corresponding to a desired conductive pattern. The metal layer is then etched through the photoresist mask to form the conductive pattern comprising metal features separated by gaps, such as a plurality of metal lines with interwiring spacings therebetween. A dielectric layer is then applied to the resulting conductive pattern to fill in the gaps and the surface is planarized, as by conventional etching or chemical-mechanical polishing (CMP) planarization techniques.
As shown in
FIGS. 1 and 2
, conventional practices comprise depositing metal layer
11
on dielectric layer
10
which is typically formed on a semiconductor substrate containing an active region with transistors (not shown). After photolithography, etching is then conducted to form a patterned metal layer comprising metal features
11
a
,
11
b,
11
c
and
11
d
with gaps therebetween. A dielectric material
12
, such as spin on glass (SOG), is typically deposited to fill in the gaps between the metal features, and baked at a temperature of about 300° C. to about 350° C., and then cured in a verticle furnace at about 350° C. to about 400° C. for a period of time up to about one hour, depending upon the particular SOG material employed, to effect planarization. Another oxide is deposited by plasma enhanced chemical vapor deposition (PECVD) and then planarization is then performed, as by CMP.
A through-hole is then formed in a dielectric layer to expose an underlying metal feature, wherein the metal feature serves as a landing pad occupying the entire bottom of the through-hole. Upon filling the through-hole with conductive material, such as a metal plug to form a conductive via, the entire bottom surface of the conductive via is in direct contact with the metal feature. Such a conventional technique is illustrated in
FIG. 3
, wherein metal feature
30
of a first patterned metal layer is formed on first dielectric layer
31
and exposed by through-hole
32
formed in second dielectric layer
33
. In accordance with conventional practices, through-hole
32
is formed so that metal feature
30
encloses the entire bottom opening, thereby serving as a landing pad for metal plug
34
which fills through-hole
32
to form conductive via
35
. Thus, the entire bottom surface of conductive via
35
is in direct contact with metal feature
30
. Conductive via
35
electrically connects metal feature
30
and metal feature
36
which is part of a second patterned metal layer. As shown in
FIGS. 2 and 3
, the side edges of a metal feature or conductive line, e.g.,
30
A,
30
B, and
36
A, and
36
B, taper somewhat as a result of etching.
The reduction of design features to the range of 0.25 microns and under requires extremely high densification. The conventional practice of forming a landing pad completely enclosing the bottom surface of a conductive via utilizes a significant amount of precious real estate on a semiconductor chip which is antithetic to escalating high densification requirements. In addition, it is extremely difficult to voidlessly fill through-holes having such reduced dimensions because of the extremely high aspect ratio, i.e., height/width of the through-hole opening. Accordingly, conventional remedial techniques comprise purposely widening the diameter of the through-hole to decrease the aspect ratio. As a result, misalignment occurs wherein the bottom surface of the conductive via is not completely enclosed by the underlying metal feature. This type of via is called a “borderless via”, which also conserves chip real estate.
The use of borderless vias, however, creates new problems. For example, as a result of misalignment, the SOG gap filling layer is penetrated by etching when forming a misaligned through-hole, due to the low density and poor stability of SOG. As a result of such penetration, moisture and gas accumulate thereby increasing the resistance of the interconnection. Moreover, spiking can occur, i.e., penetration of the metal plug to the substrate causing a short. Adverting to
FIG. 4
, first dielectric layer
41
is formed on substrate
40
and a first metal pattern comprising a first metal feature, e.g., metal line
45
, comprising anti-reflective coating
45
A, is formed on first dielectric layer
41
gap filled with SOG
42
. Dielectric layer
43
is then deposited and a misaligned through-hole formed therein exposing a portion of the upper surface and at least a portion of a side surface of metal line
45
, and penetrating into and exposing a portion of SOG layer
42
. Upon filling the through-hole with a metallic plug
44
, typically comprising an initial barrier layer (not shown) and tungsten, spiking occurs, i.e., penetration through to substrate
40
, thereby causing shorting.
Hydrogen silsesquioxane (HSQ) offers many advantages for use in interconnect patterns. HSQ is relatively carbon free, thereby avoiding poison via problems. Moreover, due to the virtual absence of carbon, it is not necessary to etch back HSQ below the upper surface of the metal lines to avoid shorting. In addition, HSQ exhibits excellent planarity and is capable of gap filling interwiring spacings less than 0.30 microns employing conventional spin-on equipment. HSQ undergoes a melting phase at approximately 200° C., but does not convert to the high dielectric constant glass phase until reaching temperatures of about 400° C. for intermetal applications and about 700° C. to about 800° C. for premetal applications.
However, HSQ is susceptible to degradation during processing leading to various problems, such as voids when forming borderless vias. For example, when forming a borderless via, a photoresist mask is deposited and the misaligned through-hole etched to expose a portion of an upper surface and a portion of a side surface of a metal line, and penetrate into and expose the HSQ layer. The photoresist mask is then stripped, typically employing an oxygen (O
2
)-containing plasma. Subsequently, solvent cleaning is performed and a second plasma stripping is conducted, also typically employing an O
2
-containing plasma. It was found that the O
2
-containing plasma employed to strip the photoresist mask, as well as the second plasma stripping subsequent to solvent cleaning, degraded the HSQ layer. Upon subsequent filling of the misaligned through-hole, as with a barrier material, such as titanium nitride or titanium-titanium nitride, spiking occurred, i.e., the barrier material penetrated through the HSQ layer to the substrate or underlying conductive feature.
HSQ typically contains between about 70% and about 90% Si—H bonds. However, upon exposure to an O
2
-containing plasma, a conside

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