4. Textiles: manufacturing

Fumihiro Kimura

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Area ratio/occupancy ratio verification method and pattern...

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate

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Carbonless copying paper

Textiles: manufacturing
Patent

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Interconnect structure of semiconductor integrated circuit,...

Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Layout editor
Reexamination Certificate

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LSI wire length estimation and area estimation

Patent

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Method of layout for LSI

Semiconductor device manufacturing: process – Making device array and selectively interconnecting – With electrical circuit layout
Reexamination Certificate

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Profile ID: LFUS-PAI-P-153551

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