Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Layout editor
Reexamination Certificate
2011-03-22
2011-03-22
Lin, Sun J (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Integrated circuit design processing
Layout editor
C716S126000, C716S129000
Reexamination Certificate
active
07913221
ABSTRACT:
A method for designing an interconnect structure of an interconnect layer in a semiconductor integrated circuit device includes the steps of: (a) inputting layout data of the semiconductor integrated circuit device; (b) controlling an air gap exclusion area based interconnects in the layout data; and (c) outputting layout data including the air gap exclusion area determined in the step (b).
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Gou Tatsuo
Hashimoto Yukiji
Iwauchi Nobuyuki
Kabuo Chie
Kimura Fumihiro
Lin Sun J
McDermott Will & Emery LLP
Panasonic Corporation
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