LSI wire length estimation and area estimation

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39550023, G06F 1750

Patent

active

059785721

ABSTRACT:
The wire length of an LSI is estimated from a netlist describing connection information of the LSI and a cell library storing information as to cells used in the LSI design, with performing no rough placement and rough wiring by a layout system. Information necessary for wire length estimation is extracted from the netlist and the cell library. A net basic wire length is determined for each fan-out. In a net wire length estimating step, a net wire length for each fan-out is estimated by making reference to the determined net basic wire length and taking into account net expansion due to the cell distribution in a cell placement. Additionally, taking into account a terminal distribution and the aspect ratio of an estimation-target block, a correction on the estimated net wire length is made. From the corrected net wire length, the total wire length of the estimation-target block is estimated.

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patent: 5774371 (1998-06-01), Kawakami
C. Sechen, "Average Interconnection Length Estimation for Random and Optimized Placements", Proc of IEEE, pp. 190-193, 1987.
M. Pedram, et al., "Interconnection Length Estimation for Optimized Standard Cell Layouts", Proc of IEEE, pp. 390-393, 1989.
T. Hamada, et al., "A Wire Length Estimation Technique Utilizing Neighborhood Density Equations", 29th ACM/IEEE Design Automation Conference, pp. 57-61, 1992.

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