Semiconductor device manufacturing: process – Making device array and selectively interconnecting – With electrical circuit layout
Reexamination Certificate
2000-07-10
2002-08-27
Sherry, Michael (Department: 2829)
Semiconductor device manufacturing: process
Making device array and selectively interconnecting
With electrical circuit layout
C716S030000, C716S030000
Reexamination Certificate
active
06440780
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a layout design method of a semiconductor integrated circuit device with low power consumption, in particular, to a layout method of a semiconductor integrated circuit device having a gated clock circuit.
2. Description of Related Arts
Semiconductor integrated circuit devices, which have recently been increasing in scale and progressing to enable faster speeds, are generally designed as a clock synchronization circuit, of which the power consumption has been increased at the clock signal part. As a method which is effective to reduce the power consumption of the clock signal part, a gated clock circuit method has been proposed.
As shown in
FIG. 33A
, a conventional clock circuit has a flip-flop FF connected directly to a clock source CS. Contrary to this, as shown in
FIG. 33B
, a gated clock circuit has a gated cell (hereinafter referred to as a “gated cell”) GC which has, as an input, at least a control signal for controlling the supply of a clock signal (hereinafter referred to as an “enabling signal”) and a clock signal, between the clock source CS and the flip-flop FF, for the purpose of stopping the supply of the clock signal to the flip-flop FF which doesn't operate under intended conditions. And the number of the flip-flops FF which can be controlled by each gated cell GC of the gated clock circuit becomes inconstant due to differences depending on the circuit. Here, the gated circuit GX is a circuit where the gated cell GC and the flip-flop FF connected to this gated cell GC are integrated.
On the other hand, in a semiconductor integrated circuit device for clock synchronization, in the case that the delay time difference of clock signals between flip-flops to which the clock signals are supplied (hereinafter referred to as “skew”) is large, the problem occurs that the semiconductor integrated circuit device doesn't operate or operates incorrectly.
Therefore, in a conventional clock circuit as shown in
FIG. 33A
, a layout method of a semiconductor integrated circuit device referred to as a “clock tree synthesis system” (hereinafter abbreviated as “CTS”) is widely used in order to generally reduce the skew of the clock signal. For example, as a layout method of the semiconductor integrated circuit device of a “clock tree synthesis system,” “An Exact Zero-Skew Clock Routing Algorithm” (IEEE Trans. Computer-Aided Design, vol. 12 no. 2, pp. 242-249, February 1993) is proposed.
A layout method of the semiconductor integrated circuit device of a “clock tree synthesis system,” is described with respect to
FIG. 34A
showing the placement result of the clock circuit in FIG.
33
A.
The layout method of the semiconductor integrated circuit device of the “clock tree synthesis system” has the purpose of implementing a circuit wherein the delay time from the clock source CS to each flip-flop FF becomes minimum and the skew becomes minimum. Therefore, based on the placement result of the flip-flop FF belonging to a clock net, a clustering is performed for division into a plurality of clusters CL surrounded by thin lines in
FIG. 34B
by utilizing an evaluation function wherein the sum of “an input capacitance of the flip-flop” forming each cluster and “a wire capacitance between flip-flops estimated according to the routing algorithm” is uniform and the sum of the entire capacitance of clusters becomes minimum. Then a buffer cell AGO
1
is inserted, which is a cell that is driven without changing its logic, into a position, for example the center or the center of the gravity of the cluster CL, where the load capacitance (including the wire capacitance) of each flip-flop FF belonging to the cluster CL, for the purpose of reducing the delay time of the clock and the skew.
Clustering is carried out, for example, as follows. Initial clusters are formed of a plurality of clusters divided by repeating the division processing into halves with respect to the flip-flop to which a clock signal should be supplied in the same way as to a conventional cluster. Next, two arbitrary clusters are selected from the initial two clusters and one arbitrary cell belonging to each of the selected clusters is selected, respectively, and interchanged with each other. In the case that the clusters resulting from the interchange satisfy the evaluation function where the sum of “an input capacitance of the flip-flop” forming each cluster and “a wire capacitance between flip-flops estimated according to the wire algorithm” is uniform and the sum of the capacities of the whole cluster become minimum, the condition where the interchange of the cells has been carried out is maintained, while in the case that the evaluation function is not satisfied, the cells are returned to the original clusters. The desired clusters can be gained by sufficiently repeating the process of clustering by using simulated annealing or the like in order to avoid the influence, or the minimum solution, of the initial clusters. The placement result after clustering is shown in FIG.
34
B.
Next, clustering and buffer insertion processing are carried out repeatedly in the same way as above to the inserted buffer cells. The placement result of carrying out clustering to the inserted buffer cells AGO
1
is shown in FIG.
34
C. The reference symbol AGO
2
denotes a buffer cell inserted at the time of clustering of the buffer cell AGO
1
.
A hierarchical tree referred to as a clock tree is generated according to the above processes. A clock circuit gained by performing a layout method of the semiconductor integrated circuit device of the “clock tree system” to the clock circuit in
FIG. 33A
is shown in FIG.
35
.
Then after routing is performed to the generated clock tree so that the wire length for each cluster becomes uniform, the entire routing except for the clock tree is completed according to the net list.
By performing the clustering processing and the routing processing described above the skew of the clock signals from the clock source CS to each of the flip-flops FF is reduced.
In the case that the “clock tree system” layout method of the semiconductor integrated circuit device according to the prior art is applied to the gated clock circuit, however, the skew between respective flip-flops cannot be reduced from the clock source via the gated cell though the skew between respective, gated cells can be reduced from the clock source.
Therefore, as a method for reducing the skew of the clock signal of the gated clock circuit, a method disclosed in, for example, the Japanese unexamined patent publication H10 (1998)-308450 or the Japanese unexamined patent publication H11 (1999)-119853 has been proposed. In comparison to the circuit of
FIG. 36
showing a gated clock circuit, a circuit implementing a method in the Japanese patent publication H10 (1998)-308456 is shown in
FIG. 7
while the result of clock tree insertion is shown in FIG.
38
. The reference symbols En
1
and En
2
show enabling signals which are added to the gated cell GC in
FIGS. 36
,
37
and
38
. The reference symbol IC denotes an inverter cell.
In the method of the Japanese unexamined patent publication H10 (1998)-308450, a placement region for a circuit GX (hereinafter referred to as a “gated circuit”) comprising each gated cell GC of the gated clock circuit and a flip-flop FF connected to each gated cell GC are designated for the placement where gated cells GC forming the gated circuit and the flip-flop FF are united in one place. Next, for each gated circuit GX, clustering is carried out so that the load capacities of the whole cluster become uniform in the same way as the clustering for a layout method of the semiconductor integrated circuit device of the conventional “clock tree system” for the division into a plurality of clusters. Then the same number of gated cells GC as the number of clusters gained through division are inserted into the geometric center of each cluster. The inserted gated cell GC is connected to the same enabling signal that the gated cell G
Ichinomiya Takahiro
Kimura Fumihiro
Pert Evan
Sherry Michael
Stevens Davis Miller & Mosher LLP
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