Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-09-11
2007-09-11
Do, Thuan (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
10886704
ABSTRACT:
Verification of the pattern area ratio of a semiconductor integrated circuit device or the pattern occupancy ratio in a check window set for the semiconductor integrated circuit device is performed on an assumption that a dummy pattern defined by process conditions is placed in an unoccupied region of the semiconductor integrated circuit device or in an unoccupied region in at least one instance provided in the semiconductor integrated circuit device.
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Ito Mitsumi
Kimura Fumihiro
Mukai Kiyohito
Shimada Jun'ichi
Do Thuan
Levin Naum
McDermott Will & Emery LLP
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