4. Static information storage and retrieval
  5. Read/write circuit
  6. Bad bit

Charles Porter Geer

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Architecture for a physical interface of a high speed front...

Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis – Multiple or variable intervals or frequencies
Reexamination Certificate

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Architecture for a physical interface of a high speed front...

Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis – Multiple or variable intervals or frequencies
Reexamination Certificate

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Clock frequency detect with programmable jitter tolerance

Miscellaneous active electrical nonlinear devices – circuits – and – Specific signal discriminating without subsequent control – By phase
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Dynamic clock phase alignment between independent clock domains

Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis
Reexamination Certificate

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Dynamic repair of redundant memory array

Static information storage and retrieval – Read/write circuit – Bad bit
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Profile ID: LFUS-PAI-P-2095433

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