Clock frequency detect with programmable jitter tolerance

Details Clock frequency detect with programmable jitter tolerance Clock frequency detect with programmable jitter tolerance

2006-10-31

2006-10-31

Nguyen, Linh My (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By phase

C327S024000

Reexamination Certificate

active

07129757

ABSTRACT:
An apparatus and method is disclosed for programmable determination of frequency, phase, and jitter relationship of a first clock and a second clock in an electronic system. In a first, initialization, mode, a first register and a second register are initialized with a first bit pattern and a second bit pattern, respectively. In a second, normal, mode, the first clock is coupled to the first register and the second clock is coupled to the second register. A compare unit observes the bit patterns of the first and second registers and reports when one or more predetermined relationships between the first clock and the second clock occur.

REFERENCES:
patent: 6034554 (2000-03-01), Francis et al.
patent: 6392494 (2002-05-01), Takeyabu et al.
patent: 6418502 (2002-07-01), Larson
patent: 7015726 (2006-03-01), Tayler et al.

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