Dynamic repair of redundant memory array

Details Dynamic repair of redundant memory array Dynamic repair of redundant memory array

1999-11-12

2001-01-30

Nguyen, Viet Q. (Department: 2818)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S225700, C365S201000, C714S006130, C714S006130, C714S710000, C714S718000, C714S733000

Reexamination Certificate

active

06181614

ABSTRACT:

FIELD OF THE INVENTION
The invention is generally related to data storage in data processing systems and the like, and in particular, to the repair of faulty memory cells in solid state memory arrays.
BACKGROUND OF THE INVENTION
Solid state memory arrays are frequently used in computers and other electronic devices where fast access times are desired. For example, solid state memory arrays are often used as the main working storage repository for a computer, as well as in higher speed cache memories, implemented either separate from or in the same integrated circuit device as the principal processing circuitry for the computer.
Solid state memory arrays are typically implemented on a semiconductor integrated circuit device using multiple memory “cells” assigned to different memory addresses and arranged together with support circuitry suitable for accessing specific memory cells in the array. Due to processing variations that are inherent in all semiconductor manufacturing processes, it is not uncommon for one or more memory cells in a manufactured memory array to be faulty, and thus be incapable of reliably storing information. While a memory array may contain thousands or millions of memory cells, if even one memory cell in the memory array is faulty, the entire memory array is essentially unusable.
To address this concern, a portion of the memory cells in many memory array designs are designated as “redundant” memory cells that are selectively used to repair the memory arrays whenever primary memory cells are found to be faulty. Typically, such repairs are made by selectively activating “fuses” disposed on the same integrated circuit device as a memory array. Often, a fuse is implemented as an conductive interconnect that is selectively (and permanently) broken using a laser or an excessive electrical current. The fuse is coupled to routing logic for the memory array, such that, when the fuse conducts, a primary memory cell, or bank of primary memory cells, are accessed whenever a specific memory address associated with such a cell is requested. However, whenever the fuse is broken, the routing logic will instead access a redundant memory cell, or bank of redundant memory cells, in place of the primary memory cell(s) associated with that memory address.
Through the use of redundant memory cells, the manufacturing yield of semiconductor devices incorporating memory arrays can be significantly improved, since memory arrays containing relatively minor faults can be repaired, rather than having to be completely scrapped. Particularly when a memory array is integrated onto the same integrated circuit device as a complex and expensive logic circuit (e.g., as a level one cache for use with a microprocessor core), the cost savings associated with fuse-based repairs can be substantial.
However, even after manufacture and repair, memory arrays are capable of failure in the field, most often due to single bit errors resulting from the failure of single memory cells. To address this concern, ABIST logic is often utilized to detect additional faulty memory cells in a memory array, typically during initialization of the memory array (e.g., during power-on reset of an integrated circuit device within which the memory array is implemented). Whenever a memory cell is determined to be faulty, the memory address associated with that memory cell is marked as “bad” and not used. In some instances, simply marking a memory location as bad is sufficient until the integrated circuit device can be replaced by service personnel. In other instances, however, the computer may crash, and thus be unusable until the failed device can be replaced. Particularly in multi-user and fault-tolerant computer systems where accessibility is a paramount concern, computer crashes are extremely costly and highly undesirable.
As a result, a significant need continues to exist in the art for an improved manner of addressing memory array failures in the field.
SUMMARY OF THE INVENTION
The invention addresses these and other problems associated with the prior art by providing a circuit arrangement and method of dynamically repairing a redundant memory array in which dynamically-determined repair information, generated from a memory test performed on the redundant memory array, is utilized along with persistently-stored repair information to repair the redundant memory array. Specifically, persistent repair information (stored, for example, in fuses and/or other non-volatile storage) is retrieved, and a memory test is initiated on the redundant memory array to generate dynamic repair information associated with the redundant memory array. Both the persistent repair information, and the dynamic repair information, are then used to dynamically repair the redundant memory array.
While the invention may be utilized in a wide variety of other applications, one particularly beneficial application of the invention may be in dynamically repairing a redundant memory array during array initialization to automatically repair the array in the field. In such an implementation, the persistent repair information may be generated during manufacture to repair manufacturing defects in the array, with the dynamic repair information generated during a power-on reset to address any additional faults arising after initial manufacture and repair of the array. Typically, but not exclusively, the testing of the redundant memory array in such an implementation occurs after any faults identified by the persistent repair information are repaired, such that additional faults can be detected separate from any manufacturing faults. As a consequence, the occurrence of relatively minor faults after manufacture of an array may be repaired, rather than requiring replacement of the array in the field, potentially resulting in fewer service calls and greater reliability.
Moreover, while other manners of dynamically repairing a redundant memory array may be used consistent with the invention, one particularly beneficial implementation utilizes redundant memory cells in the memory array that would be otherwise unused after repair during manufacture. As such, additional memory cells above and beyond those required to ensure suitable manufacturing yields would typically not be required to implement dynamic repair consistent with the invention.
These and other advantages and features, which characterize the invention, are set forth in the claims annexed hereto and forming a further part hereof. However, for a better understanding of the invention, and of the advantages and objectives attained through its use, reference should be made to the Drawings, and to the accompanying descriptive matter, in which there is described exemplary embodiments of the invention.


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