Mask network design for scan-based integrated circuits

Details Mask network design for scan-based integrated circuits Mask network design for scan-based integrated circuits

2006-02-10

2010-06-08

Lin, Sun J (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C714S726000, C714S727000, C714S729000

Reexamination Certificate

active

07735049

ABSTRACT:
A method and apparatus for selectively masking off unknown (‘x’) captured scan data in first selected scan cells220from propagating through the scan chains221for test, debug, diagnosis, and yield improvement of a scan-based integrated circuit207in a selected scan-test mode232or selected self-test mode. The scan-based integrated circuit207contains a plurality of scan chains221, a plurality of pattern generators208, a plurality of pattern compactors213, with each scan chain221comprising multiple scan cells220, 222coupled in series. The method and apparatus further includes an output-mask controller211and an output-mask network212embedded on the scan data input path of second selected scan cells222, or a set/reset controller controlling selected set/reset inputs of second selected scan cells. A synthesis method is also proposed for synthesizing the output-mask controller211and the set/reset controller.

REFERENCES:
patent: 6557129 (2003-04-01), Rajski et al.
patent: 6829740 (2004-12-01), Rajski et al.
patent: 6901546 (2005-05-01), Chu et al.
patent: 7058869 (2006-06-01), Abdel-Hafez et al.
patent: 2003/0229833 (2003-12-01), Nadeau-Dostie
patent: WO 2005031378 (2005-04-01), None
Wallis, A. D. And Woodman, Jr., G. R.; Joint Test Action Group Error Injection Configuration; IBM Technical Disclosure Bulletin; Jul. 1995; vol. 38, No. 07; pp. 5-8.
Mitra et al: “X-Compact: An Efficient Response Compaction Technique for Test Cost Reduction,” Proc., IEEE Intl. Test Conf., 2002.
Mitra et al: “XMAX: X-Tolerant Architecture for MAXimal Test Compression,” Proc. Intl. Conf. On Computer Design, pp. 326-330, 2003.

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