Method of making double-poly MONOS flash EEPROM cell

Details Method of making double-poly MONOS flash EEPROM cell Method of making double-poly MONOS flash EEPROM cell

1997-06-12

1999-07-27

Booth, Richard A.

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438305, 438266, H01L 218247

Patent

active

059306319

ABSTRACT:
The present invention discloses a double poly metal oxide
itride/oxide semiconductor electrically erasable programmable read only memory (EEPROM) for use in semiconductor memories. The EEPROM structure includes a select gate, an oxide.backslash.nitride.backslash.oxide layer, and a control gate. The control gate is formed on the oxide.backslash.nitride.backslash.oxide layer. A lightly doped drain (LDD) structure is formed adjacent to the drain and underneath the control gate.

REFERENCES:
patent: 4098924 (1978-07-01), McLouski et al.
patent: 4105805 (1978-08-01), Glendinning et al.
patent: 4964080 (1990-10-01), Tzeng
patent: 5326999 (1994-07-01), Kim et al.
patent: 5700728 (1997-12-01), Kuo et al.
patent: 5851881 (1998-12-01), Lin et al.

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