Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent
1999-03-16
2000-08-01
Cady, Albert De
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
714738, G01R 3128
Patent
active
060981873
ABSTRACT:
A sufficient and necessary number of operation cycles for detecting faults, which have not been found by a function test, are accurately and rapidly selected by performing a logical simulation of an operation of an integrated circuit including m internal nets. A fault simulation is performed by using a predetermined test pattern so as to specify internal nets for which a fault is detected. Standby cycles are detected from among operation cycles in the logical simulation. .alpha. internal nets at which a fault is detected by the fault simulation from among the m internal nets to be subjected to the IDDQ test are excluded. The standby cycles are selected as the IDDQ test cycles based on the (m-.alpha.) internal nets.
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Cady Albert De
Lamarre Guy
Ricoh Co. Ltd.
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