Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent
1998-05-29
2000-08-01
De Cady, Albert
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
714735, 714741, G01R 3128
Patent
active
060981865
ABSTRACT:
Disclosed is the selecting of permutations of a plurality of parameters, each parameter comprising a plurality of parameter values, for applying the selected permutations as a permutation sequence to a device under test DUT. At first, a cycle size representing the number of parameter values in a parameter cycle to be repeated successively in the permutation sequence is defined for each parameter. The following criteria have to be met: a) the cycle sizes have to be different for all parameter cycles, b) each cycle size has to be equal or greater than the number of different parameter values of the respective parameter, and c) two cycle sizes must not have one or more factors in common. Each parameter cycle is provided with parameter values from that parameter according to the defined cycle size, and the parameter cycles can be repeated concurrently, preferably until a given termination criterion is reached all possible permutations have been selected.
REFERENCES:
patent: 5343554 (1994-08-01), Koza et al.
patent: 5621665 (1997-04-01), Ghosh et al.
patent: 5737252 (1998-04-01), Hollmann et al.
patent: 5953531 (1999-09-01), Megiddo et al.
patent: 5954662 (1999-09-01), Swanson et al.
Cady Albert De
Hewlett--Packard Company
Ton David
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