Semiconductor memory device and method

Details Semiconductor memory device and method Semiconductor memory device and method

1997-10-17

1999-03-02

Dinh, Son T.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365221, G11C 700

Patent

active

058779906

ABSTRACT:
A semiconductor memory device and method are provided that enhance data output speed of a DRAM or the like by reducing the time difference between the data output operation from a preceding word line and the data output operation from a succeeding word line. The semiconductor memory device includes a memory cell array arranged with multiple memory cells having a corresponding word line and a corresponding bit line, a row decoder for decoding a row address to select and activate a word line of the memory cell array and a sense amplifier for sensing and amplifying the data in a memory cell coupled to the activated word line when the data is applied to the corresponding bit line. The semiconductor further includes first and second latches respectively storing data using the sense amplifier taken from a memory cell coupled to a preceding activated word line and a succeeding activated word line. A switching block controls the data path between the sense amplifier and the first latch, or the sense amplifier and the second latch and a column decoder selects and applies the data stored in the first or second latch to a data bus. A data bus sense amplifier amplifies the data applied to the data bus before transmitting it to a data output buffer.

REFERENCES:
patent: 5278790 (1994-01-01), Kanabara
patent: 5517461 (1996-05-01), Unno et al.
patent: 5530955 (1996-06-01), Kaneko
patent: 5559990 (1996-09-01), Cheng et al.
patent: 5699311 (1997-12-01), Sato et al.

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