Prevention of post CMP defects in CU/FSG process

Details Prevention of post CMP defects in CU/FSG process Prevention of post CMP defects in CU/FSG process

2006-08-09

2011-11-08

Blum, David S. (Department: 2813)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S629000, C438S634000, C438S645000, C257S752000, C257SE21582

Reexamination Certificate

active

08053357

ABSTRACT:
A common problem associated with damascene structures made of copper inlaid in FSG (fluorinated silicate glass) is the formation of defects near the top surface of the structure. The present invention avoids this problem by laying down a layer of USG (undoped silicate glass) over the surface of the FSG layer prior to patterning and etching the latter to form the via hole and (for a dual damascene structure) the trench. After over-filling with copper, the structure is planarized using CMP. The USG layer acts both to prevent any fluorine from the FSG layer from reaching the copper and as an end-point detector during CMP. In this way defects that result from copper-fluorine interaction do not form and precise planarization is achieved.

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