Memory having sense time of variable duration

Details Memory having sense time of variable duration Memory having sense time of variable duration

2006-08-11

2010-02-23

Ho, Hoai V (Department: 2827)

Static information storage and retrieval

Read/write circuit

Precharge

C365S191000, C365S207000, C365S233100

Reexamination Certificate

active

07668029

ABSTRACT:
In one form a memory and method thereof has a memory array having a plurality of memory cells. A bit line precharge operation is based on a clock edge of an external clock signal. A word line is selected after the beginning of the precharge operation. A sense operation is begun after enabling the word line, where the sense operation is for sensing a logic state of a memory cell. A data bit is output from the memory array corresponding to the sensed logic state of the memory cell. In one form the bit line precharge operation further comprises the bit line precharge operation having a predetermined duration that is independent of the clock signal, and the sense operation begins a predetermined delay time after enabling the word line, the sense operation having a variable duration.

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