Semiconductor packages, stacked semiconductor packages, and...

Details Semiconductor packages, stacked semiconductor packages, and... Semiconductor packages, stacked semiconductor packages, and...

2007-12-28

2010-11-02

Blum, David S (Department: 2813)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S689000, C257S777000, C257SE21001, C257SE23141

Reexamination Certificate

active

07825468

ABSTRACT:
A semiconductor package may include a semiconductor pattern, a bonding pad, and a polymer insulation member. The semiconductor pattern may include a semiconductor device and first hole. The bonding pad may include a wiring pattern and plug. The wiring pattern may be formed on an upper face of the semiconductor pattern. The plug may extend from the wiring pattern to fill the first hole. The polymer insulation member may be formed on a lower face of the semiconductor pattern and may include a second hole exposing a lower end of the plug. A method of manufacturing a semiconductor package may include forming a first hole through a semiconductor substrate; forming a bonding pad and plug; attaching a supporting member to the upper face of the substrate; reducing a thickness of the substrate; forming a polymer insulation member on the lower face of the substrate; and cutting the substrate.

REFERENCES:
patent: 5153986 (1992-10-01), Brauer et al.
patent: 7127301 (2006-10-01), Okandan et al.
patent: 2005/0224952 (2005-10-01), Vindasius et al.
patent: 2006/0055050 (2006-03-01), Numata et al.
patent: 2006/0131721 (2006-06-01), Ito
patent: 2002-050738 (2002-02-01), None
patent: 2004-228392 (2004-08-01), None
patent: 2004-288722 (2004-10-01), None
patent: 10-2006-0051152 (2006-05-01), None
Korean Patent Office Action dated Jan. 15, 2008, for Korean Patent Application No. 10-2006-0137859 (3 pp.).

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