Testing a circuit with compressed scan chain subsets

Details Testing a circuit with compressed scan chain subsets Testing a circuit with compressed scan chain subsets

2007-10-23

2010-11-09

Trimmings, John P (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S025000, C714S030000, C714S726000, C714S727000

Reexamination Certificate

active

07831876

ABSTRACT:
A test system tests a circuit. Compressed scan data subsets are stored, one at a time, in a memory of the test system. The multiple compressed scan data subsets correspond with multiple scan chains in a function block of the tested circuit. Transmission of the compressed scan data subset from the memory to the tested circuit is controlled by the test system. The test system receives a compacted test output subset from the tested circuit and provides a test system output that indicates a presence of any errors in functioning of the tested circuit.

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