High density stepped, non-planar flash memory

Details High density stepped, non-planar flash memory High density stepped, non-planar flash memory

2006-06-22

2009-06-23

Nguyen, Thinh T (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S257000, C438S259000, C257S314000, C257S315000

Reexamination Certificate

active

07550341

ABSTRACT:
A first plurality of memory cells is in a first plane in a first column of the array. A second plurality of memory cells is in a second plane in the same column. The second plurality of memory cells are coupled to the first plurality of memory cells through a series connection of their source/drain regions.

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