Diffusion layer for stressed semiconductor devices

Details Diffusion layer for stressed semiconductor devices Diffusion layer for stressed semiconductor devices

2006-02-14

2009-10-27

Lebentritt, Michael S (Department: 2829)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S300000, C438S429000, C438S430000, C438S589000, C438S607000, C257SE21133, C257SE21409, C257SE21431, C257SE21633, C257SE21644, C257SE29040, C257SE29063, C257SE29084, C257SE29121, C257SE29267

Reexamination Certificate

active

07608515

ABSTRACT:
A diffusion layer for semiconductor devices is provided. In accordance with embodiments of the present invention, a semiconductor device, such as a transistor, comprises doped regions surrounded by a diffusion barrier. The diffusion barrier may be formed by recessing regions of the substrate and implanting fluorine or carbon ions. A silicon layer may be epitaxially grown over the diffusion barrier in the recessed regions. Thereafter, the recessed regions may be filled and doped with a semiconductor or semiconductor alloy material. In an embodiment, a semiconductor alloy material, such as silicon carbon, is selected to induce a tensile stress in the channel region for an NMOS device, and a semiconductor alloy material, such as silicon germanium, is selected to induce a compressive stress in the channel region for a PMOS device.

REFERENCES:
patent: 5132768 (1992-07-01), Jaecklin et al.
patent: 5312768 (1994-05-01), Gonzalez
patent: 5908313 (1999-06-01), Chau et al.
patent: 6492216 (2002-12-01), Yeo et al.
patent: 6635543 (2003-10-01), Furukawa et al.
patent: 6653856 (2003-11-01), Liu
patent: 6762463 (2004-07-01), Kim
patent: 6762961 (2004-07-01), Eleyan et al.
patent: 6815970 (2004-11-01), Rost et al.
patent: 6846720 (2005-01-01), Balasubramanian et al.
patent: 6887762 (2005-05-01), Murthy et al.
patent: 6905918 (2005-06-01), Mouli
patent: 6921913 (2005-07-01), Yeo et al.
patent: 7105897 (2006-09-01), Chen et al.
patent: 7112495 (2006-09-01), Ko et al.
patent: 7129548 (2006-10-01), Chan et al.
patent: 7132338 (2006-11-01), Samoilov et al.
patent: 7358551 (2008-04-01), Chidambarrao et al.
patent: 7413961 (2008-08-01), Chong et al.
patent: 7436026 (2008-10-01), Kreps
patent: 7436035 (2008-10-01), Murthy et al.
patent: 2004/0166611 (2004-08-01), Liu
patent: 2005/0045951 (2005-03-01), Yamada et al.
patent: 2007/0072353 (2007-03-01), Wu et al.
Chen, G., et al., “Dynamic NBTI of p-MOS Transistors and Its Impact on MOSFET Scaling,” IEEE Electron Device Letters (2002) pp. 1-3.
El Mubarek, H. A. W., et al., “Effect of Fluorine Implantation Dose on Boron Transient Enhanced Diffusion and Boron Thermal Diffusion in Si1-xGex,” IEEE Transactions on Electron Devices, vol. 52, No. 4 (Apr. 2005) pp. 518-526.
Fenouillet-Beranger, C., et al., “Requirements for ultra-thin-film devices and new materials on CMOS Roadmap,” IEEE, 2003, pp. 145-146.
Fukada, Y., et al., “Special Edition on 21stCentury Solutions: SOI-CMOS Device Technology,” OKI Technical Review 185, vol. 68, Mar. 2001, pp. 54-57.
Koh, R., “Buried Layer Engineering to Reduce the Drain-Induced Barrier Lowering of Sub-0.05 μm SOI-MOSFET,” Jpn. J. Appl. Phys., vol. 38, 1999, pp. 2294-2299.
Roche, P., et al., “Comparisons of Soft Error Rate for SRAMs in Commercial SOI and Bulk Below the 130-nm Technology Node,” IEEE Transactions on Nuclear Science, vol. 50, No. 6, Dec. 2003, pp. 2046-2054.
Mandelman, J.A., et al., “Floating-Body Concerns for SOI Dynamic Random Access Memory (DRAM),” Proceedings of the IEEE International SOI Conference, Oct. 1996, pp. 136-137.
Yang, M., et al., “High Performance CMOS Fabricated on Hybrid Substrate With Different Crystal Orientations,” IEDM, 2003, pp. 453-456.
Rim, K., et al., “Fabrication and Mobility Characteristics of Ultra-thin Strained Si Directly on Insulator (SSDOI) MOSFETs,” IEDM, 2003, pp. 49-52.

Affiliated with

Also associated with

Rating

Diffusion layer for stressed semiconductor devices does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Diffusion layer for stressed semiconductor devices, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Diffusion layer for stressed semiconductor devices will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4093620