Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2006-08-11
2009-06-02
Parker, Kenneth A (Department: 2815)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S769000, C438S770000, C438S774000, C438S775000, C438S785000, C257S411000, C257SE21194, C257SE21276
Reexamination Certificate
active
07541246
ABSTRACT:
A gate insulating film and a gate electrode are formed on a silicon substrate. The gate insulating film contains at least hafnium, oxygen, fluorine, and nitrogen. The fluorine concentration is high in the vicinity of an interface with the silicon substrate and progressively decreases with decreasing distance from the gate electrode. The nitrogen concentration is high in the vicinity of an interface with the gate electrode and progressively decreases with decreasing distance from the silicon substrate. The fluorine concentration in the vicinity of the interface with the silicon substrate is preferably 1×1019cm−3or more. The nitrogen concentration in the vicinity of the interface with the gate electrode is preferably 1×1020cm−3or more.
REFERENCES:
patent: 5712208 (1998-01-01), Tseng et al.
patent: 6191463 (2001-02-01), Mitani et al.
patent: 6642131 (2003-11-01), Harada
patent: 6700170 (2004-03-01), Morosawa et al.
patent: 6784508 (2004-08-01), Tsunashima et al.
patent: 7002224 (2006-02-01), Li
patent: 2004/0084736 (2004-05-01), Harada
patent: 08-316465 (1996-11-01), None
patent: 11-97683 (1999-04-01), None
patent: 2000-243960 (2000-09-01), None
patent: 2001-257344 (2001-09-01), None
patent: 2003-8011 (2003-01-01), None
patent: 2003-318176 (2003-11-01), None
Schroder et al., “Negative bias temperature instability: Road to cross in deep submicron silicon semiconductor manufacturing”, Journal of Applied Physics, Jul. 1, 2003, pp. 1-18, vol. 94, No. 1.
Quevedo-Lopez et al., “Effect of N incorporation on boron penetration from p+ polycrystalline-Si through HfSixOy films”, Applied Physics Letters, Jun. 30, 2003, pp. 4669-4671, vol. 82, No. 26.
“Process Integration, Devices, and Structures”, The International Technology Roadmap for Semiconductors: 2003, p. 199, 203, 205.
Sasaki Takaoki
Tamura Yasuyuki
Diaz José R
Fujitsu Limited
Leydig , Voit & Mayer, Ltd.
Parker Kenneth A
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