Methods of manufacturing multiple gate CMOS transistors...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C257S274000

Reexamination Certificate

active

07462538

ABSTRACT:
Semiconductor devices with transistors having different gate dielectric materials and methods of manufacture thereof are disclosed. One embodiment includes a semiconductor device including a workpiece, the workpiece including a first region and a second region proximate the first region. A first transistor is disposed in the first region of the workpiece, the first transistor having at least two first gate electrodes. A first gate dielectric is disposed proximate each of the at least two first gate electrodes, the first gate dielectric comprising a first material. A second transistor is disposed in the second region of the workpiece, the second transistor having at least two second gate electrodes. A second gate dielectric is disposed proximate each of the at least two second gate electrodes, the second gate dielectric comprising a second material. The second material is different than the first material.

REFERENCES:
patent: 4432035 (1984-02-01), Hsieh et al.
patent: 4990974 (1991-02-01), Vinal
patent: 5041885 (1991-08-01), Gualandris et al.
patent: 5066995 (1991-11-01), Young et al.
patent: 5162263 (1992-11-01), Kunishima et al.
patent: 5321287 (1994-06-01), Uemura et al.
patent: 5763922 (1998-06-01), Chau
patent: 5994747 (1999-11-01), Wu
patent: 6020243 (2000-02-01), Wallace et al.
patent: 6027961 (2000-02-01), Maiti et al.
patent: 6048769 (2000-04-01), Chau
patent: 6084280 (2000-07-01), Gardner et al.
patent: 6124171 (2000-09-01), Arghavani et al.
patent: 6159782 (2000-12-01), Xiang et al.
patent: 6184072 (2001-02-01), Kaushik et al.
patent: 6225163 (2001-05-01), Bergemont
patent: 6291867 (2001-09-01), Wallace et al.
patent: 6348390 (2002-02-01), Wu
patent: 6410967 (2002-06-01), Hause et al.
patent: 6444555 (2002-09-01), Ibok
patent: 6475908 (2002-11-01), Lin et al.
patent: 6492217 (2002-12-01), Bai et al.
patent: 6528858 (2003-03-01), Yu et al.
patent: 6656764 (2003-12-01), Wang et al.
patent: 6716685 (2004-04-01), Lahaug
patent: 6720221 (2004-04-01), Ahn et al.
patent: 6737313 (2004-05-01), Marsh et al.
patent: 6740944 (2004-05-01), McElheny et al.
patent: 6852645 (2005-02-01), Colombo et al.
patent: 6897095 (2005-05-01), Adetutu et al.
patent: 6921691 (2005-07-01), Li et al.
patent: 7060568 (2006-06-01), Metz et al.
patent: 7091568 (2006-08-01), Hegde et al.
patent: 2002/0005556 (2002-01-01), Cartier et al.
patent: 2002/0053711 (2002-05-01), Chau et al.
patent: 2002/0135030 (2002-09-01), Horikawa
patent: 2002/0135048 (2002-09-01), Ahn et al.
patent: 2002/0151125 (2002-10-01), Kim et al.
patent: 2002/0153573 (2002-10-01), Mogami
patent: 2003/0057432 (2003-03-01), Gardner et al.
patent: 2003/0104663 (2003-06-01), Visokay et al.
patent: 2003/0116804 (2003-06-01), Visokay et al.
patent: 2003/0137017 (2003-07-01), Hisamoto et al.
patent: 2003/0141560 (2003-07-01), Sun
patent: 2003/0219953 (2003-11-01), Mayuzumi
patent: 2004/0000695 (2004-01-01), Matsuo
patent: 2004/0005749 (2004-01-01), Choi et al.
patent: 2004/0009675 (2004-01-01), Eissa et al.
patent: 2004/0023462 (2004-02-01), Rotondaro et al.
patent: 2004/0132271 (2004-07-01), Ang et al.
patent: 2004/0180487 (2004-09-01), Eppich et al.
patent: 2004/0217429 (2004-11-01), Lin et al.
patent: 2004/0242021 (2004-12-01), Kraus et al.
patent: 2005/0035345 (2005-02-01), Lin et al.
patent: 2005/0045965 (2005-03-01), Lin et al.
patent: 2005/0064663 (2005-03-01), Saito
patent: 2005/0098839 (2005-05-01), Lee et al.
patent: 2005/0101159 (2005-05-01), Droopad
patent: 2005/0139926 (2005-06-01), Shimizu et al.
patent: 2005/0148137 (2005-07-01), Brask et al.
patent: 2005/0167750 (2005-08-01), Yang et al.
patent: 2005/0224897 (2005-10-01), Chen et al.
patent: 2005/0245019 (2005-11-01), Luo et al.
patent: 2005/0280104 (2005-12-01), Li
patent: 2006/0003507 (2006-01-01), Jung et al.
patent: 2006/0017112 (2006-01-01), Wang et al.
patent: 2006/0038236 (2006-02-01), Yamamoto
patent: 2006/0118879 (2006-06-01), Li
patent: 2006/0131652 (2006-06-01), Li
patent: 2006/0141729 (2006-06-01), Wang et al.
patent: 2006/0211195 (2006-09-01), Luan
patent: 2006/0223335 (2006-10-01), Mathew et al.
patent: 2006/0275975 (2006-12-01), Yeh et al.
patent: 2007/0018245 (2007-01-01), Jeng
patent: 2007/0034945 (2007-02-01), Bohr et al.
patent: 1 388 889 (2004-02-01), None
patent: 1 531 496 (2005-05-01), None
patent: 2002118175 (2002-04-01), None
patent: 2004289061 (2004-10-01), None
patent: WO 01/66832 (2001-09-01), None
patent: WO 2004/095556 (2004-11-01), None
patent: WO 2005/114718 (2005-12-01), None
patent: WO 2006/061371 (2006-06-01), None
patent: WO 2006/067107 (2006-06-01), None
Wakabayashi, H., et al., “A Dual-Metal Gate CMOS Technology Using Nitrogen-Concentration-Controlled TiNx Film,” IEEE Transactions on Electron Devices, Oct. 2001, pp. 2363-2369, vol. 48, No. 10, IEEE, Los Alamitos, CA.
Hobbs, C.C., et al., “Fermi-Level Pinning at the Polysilicon/Metal Oxide Interface—Part I,” IEEE Transactions on Electron Devices, vol. 51, No. 6, Jun. 2004, pp. 971-977.
Li, H.-J., et al., “Dual High-k Gate Dielectric With Poly Gate Electrode: HfSiON on nMOS and Al2O3Capping Layer on pMOS,” IEEE Electron Device Letters, Jul. 2005, pp. 441-444, vol. 26, No. 7, IEEE.
Choi, Y-K., et al., “FinFET Process Refinements for Improved Mobility and Gate Work Function Engineering,” IEDM, 2002, pp. 259-262, IEEE, Los Alamitos, CA.
Choi, Y-K, et al., “Sub-20nm CMOS FinFET Technologies,” IEDM, 2001, pp. 421-424, IEEE, Los Alamitos, CA.
Lin, R., et al., “An Adjustable Work Function Technology Using Mo Gate for CMOS Devices,” IEEE Electron Device Letters, Jan. 2002, pp. 49-51, vol. 23, No. 1, IEEE, Los Alamitos, CA.
“Front End Processes,” The International Technology Roadmap for Semiconductors: 2003 Edition, pp. 23-25, http://member.itrs.net/.
Gannavaram, S., et al., “Low Temperature (≦ 800° C) Recessed Junction Selective Silicon-Germanium Source/Drain Technology for sub-70 nm CMOS,” 2000, 4 pp., IEEE, Los Alamitos, CA.
Huang, F.-J., et al., “Schottky-Clamped NMOS Transistors Implemented in a Conventional 0.8-μm CMOS Process,” IEEE Electron Device Letters, Sep. 1998, pp. 326-328, vol. 19, No. 9, IEEE, Los Alamitos, CA.
Park, D.-G., et al., “Thermally Robust Dual-Work Function ALD-MNxMOSFETs using Conventional CMOS Process Flow,” 2004 Symposium on VLSI Technology Digest of Technical Papers, 2004, pp. 186-187, IEEE, Los Alamitos, CA.
Chang, L., et al., “Extremely Scaled Silicon Nano-CMOS Devices,” Proceedings of the IEEE, Nov. 2003, vol. 91, No. 11, pp. 1860-1873, IEEE.
“Front End Processes,” The International Technology Roadmap for Semiconductors: 2002 Update, pp. 45-62, http://member.itrs.net/.
Guha, S., et al., “Atomic Beam Deposition of Lanthanum- and Yttrium-Based Oxide Thin Films for Gate Dielectrics,” Applied Physics Letters, Oct. 23, 2000, vol. 77, No. 17, pp. 2710-2712, American Institute of Physics.
“HighKDielectric Materials,” Tutorial: Materials for Thin Films / Microelectronics, downloaded Jun. 9, 2004, 3 pp., Sigma-Aldrich Co., St. Lois, Missouri, US, http://www.sigmaaldrich.com/Area—of—Interest/Organic—Inorganic—Chemistry/ Materials—Science/Thin—Films—Microelectronics/Tutorial/Dielectric—Materials.html.
Hobbs, C., et al., “Fermi Level Pinning at the PolySi/Metal Oxide Interface,” 2003 Symposium on VLSI Technology Digest of Technical Papers, Jun. 2003, 2 pp.
Muller, R.S., et al., “Device Electronics for Integrated Circuits,” Second Ed., 1986, pp. 380-385, 398-399, John Wiley & Sons, New York, NY.
Nowak, E.J., et al., “Turning Silicon on its Edge: Overcoming Silicon Scaling Barriers with Double-Gate and FinFET Technology,” IEEE Circuits & Devices Magazine, Jan./Feb. 2004, pp. 20-31, IEEE.
Samavedam, S.B., et al., “Fermi Level Pinning with Sub-Monolayer MeOx and Metal Gates,” IEEE, Mar. 2003, 4 pp.
Wolf, S., “Silicon Processing for th

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Methods of manufacturing multiple gate CMOS transistors... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Methods of manufacturing multiple gate CMOS transistors..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Methods of manufacturing multiple gate CMOS transistors... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-4023169

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.