Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2004-08-06
2008-08-26
Geyer, Scott B. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S216000, C438S288000, C438S261000, C257SE21639
Reexamination Certificate
active
07416933
ABSTRACT:
Complementary transistors and methods of forming the complementary transistors on a semiconductor assembly are described. The transistors are formed with an optional interfacial oxide, such as SiO2or oxy-nitride, to overlay a semiconductor substrate which will be conductively doped for PMOS and NMOS regions. Then a dielectric possessing a high dielectric constant of least seven or greater (also referred to as a high-k dielectric) is deposited on the interfacial oxide. The high-k dielectric is covered with a thin monolayer of metal oxide (i.e., aluminum oxide, Al2O3) that is removed from the NMOS regions, but remains in the PMOS regions. The resulting NMOS transistor diffusion regions contain predominately metal to silicon bonds that create predominately Fermi level pinning near the valence band while the resulting PMOS transistor diffusion regions contain metal to silicon bonds that create predominately Fermi level pinning near the conduction band.
REFERENCES:
patent: 6166417 (2000-12-01), Bai et al.
patent: 6492217 (2002-12-01), Bai et al.
patent: 6861304 (2005-03-01), Hisamoto et al.
patent: 6872613 (2005-03-01), Xiang et al.
patent: 6906398 (2005-06-01), Yeo et al.
patent: 7023064 (2006-04-01), Park et al.
patent: 7045847 (2006-05-01), Lin et al.
patent: 7105889 (2006-09-01), Bojarczuk et al.
patent: 2003/0137017 (2003-07-01), Hisamoto et al.
patent: 2005/0035345 (2005-02-01), Lin et al.
patent: 2005/0269634 (2005-12-01), Bojarczuk et al.
patent: 2005/0269635 (2005-12-01), Bojarczuk et al.
patent: 2005/0280099 (2005-12-01), Park et al.
patent: 2005/0280104 (2005-12-01), Li
patent: 2005/0282329 (2005-12-01), Li
patent: 2006/0040439 (2006-02-01), Park et al.
patent: 2006/0102968 (2006-05-01), Bojarczuk et al.
patent: 2006/0118879 (2006-06-01), Li
patent: 2006/0275977 (2006-12-01), Bojarczuk et al.
“Fermi-Level Pinning Induced Thermal Instability in the Effective Work Function of TaN in TaN/SiO2 Gate Stack”, C. Ren, et al., IEEE Electron Device Letters, vol. 25, No. 3, Mar. 2004, pp. 123-125.
“Effects of High-K Dielectrics on the Workfunctions of Metal and Silicon Gates”, Yee-Chia Yeo, et al., 2001 Symposium of VLSI Technology Digest of Techical Papers.
“Effect of Polycrystalline-Silicon Gate Types on the Opposite Flatband Voltage Shift in N-Type and P-Type Metal-Oxide-Semiconductor Field-Effect Transistors for High-K-HfO2 Dielectric”, C.W. Yang, et al., Applied Physics Letters, vol. 83, No. 2, Jul. 14, 2003, pp. 308-310.
“Fermi-Level Pinning at the Polysilicon/Metal-Oxide Interface—Part II”, Christopher C. Hobbs, et al., IEEE Transactions on Electron Devices, vol. 51, No. 6, Jun. 2004, pp. 978-984.
“Fermi Level Pinning at the PolySi/Metal Oxide Interface”, C. Hobbs, et al., 2003 Symposium on VLSI Technology Digest of Technical Papers.
“Fermi-Level Pinning at the Polysilicon/Metal Oxide Interface—Part I”, Christopher C. Hobbs, et al., IEEE Transactions on Electron Devices, vol. 51, No. 6, Jun. 2004, pp. 971-977.
Geyer Scott B.
Isaac Stanetta D
Micro)n Technology, Inc.
Romani Mike
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