Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2005-08-25
2008-10-14
Ton, David (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S727000
Reexamination Certificate
active
07437640
ABSTRACT:
Methods, apparatus, and systems for diagnosing failing scan cells from compressed test responses are disclosed herein. For example, in one nonlimiting exemplary embodiment, a compactor for compacting test responses in a circuit-under-test is disclosed. In this embodiment, the compactor includes an injector network comprising combinational logic and includes injector-network outputs and injector-network inputs. At least some of the injector-network inputs are logically coupled to two or more injector-network outputs according to respective injector polynomials. The exemplary compactor further comprises a selection circuit that includes selection-circuit outputs coupled to the injector-network inputs and selection-circuit inputs coupled to scan-chain outputs of the circuit-under-test. The selection circuit is configured to selectively route signals from the scan-chain outputs to the injector-network inputs according to one of plural different input configurations.
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Mrugalski Grzegorz
Pogiel Artur
Rajski Janusz
Tyszer Jerzy
Wang Chen
Klarquist & Sparkman, LLP
Ton David
LandOfFree
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