Method of forming a bit-line and a capacitor structure in an int

Details Method of forming a bit-line and a capacitor structure in an int Method of forming a bit-line and a capacitor structure in an int

1996-02-07

1998-08-11

Bowers, Jr., Charles L.

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438248, 438387, 438391, H01L 218242

Patent

active

057926867

ABSTRACT:
A dynamic random access memory (DRAM) integrated circuit (10). The DRAM (10) includes a recessed region (20) defined in a semiconductor substrate (22). This recessed region has substantially vertical sides (34) extending from a bottom surface (32). A field effect transistor (18) is defined adjacent to the recessed region (20). A capacitor structure, including a lower capacitor plate (26), a capacitor dielectric (28), and an upper capacitor plate (30), is defined in the recessed region (20) and over the field effect transistor (18), thereby providing a greater capacitor surface.

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patent: 5521111 (1996-05-01), Sato
Wolf et al.; "Chemical Vapor Deposition of Amorphous and Polycrystalline Films," Silicon Processing for the VLSI Era-vol. 1; CA, Lattice Press, 1986; pp. 181-182.

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