Method and BIST architecture for fast memory testing in...

Details Method and BIST architecture for fast memory testing in... Method and BIST architecture for fast memory testing in...

2007-05-08

2007-05-08

Lamarre, Guy (Department: 2138)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S718000, C714S736000

Reexamination Certificate

active

10999493

ABSTRACT:
The present invention provides a method and BIST architecture for fast memory testing in a platform-based integrated circuit. The method may include steps as follows. An Mem-BIST controller transmitter is started to generate input signals for a memory in a platform using a deterministic and unconditional test algorithm. The input signals are delayed by a first group of pipelines by n clock cycles. The delayed input signals are received by the memory and an output signal is generated by the memory. The output signal is delayed by a second pipeline by m clock cycles. An Mem-BIST controller receiver is started to receive the delayed output signal for comparison.

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patent: 5995731 (1999-11-01), Crouch et al.
patent: 6321320 (2001-11-01), Fleischman et al.
patent: 2002/0059543 (2002-05-01), Cheng et al.
patent: 2004/0128596 (2004-07-01), Menon et al.
patent: 2005/0066247 (2005-03-01), Cheng et al.

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