Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2007-09-18
2007-09-18
Ton, David (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S047300
Reexamination Certificate
active
10912506
ABSTRACT:
A method, apparatus, and computer instructions for monitoring a device in a data processing system. A register associated with the device is accessed from a reduced function processor core through a connection between the register for the device and the reduced function processor core. The device is monitored using the value of the register.
REFERENCES:
patent: 4310921 (1982-01-01), Rosa
patent: 6377028 (2002-04-01), Armstrong et al.
patent: 6615344 (2003-09-01), Hagen
patent: 6810338 (2004-10-01), Mercke et al.
patent: 7012924 (2006-03-01), Storck
patent: 7069176 (2006-06-01), Swaine et al.
patent: 7080283 (2006-07-01), Songer et al.
patent: 7093081 (2006-08-01), DeWitt et al.
Blanchard Anton
Miller, II Milton Devon
Venton Todd Alan
Gerhardt Diana R.
Glanzman Gerald H.
Ton David
Yee Duke W.
LandOfFree
Method and apparatus for system monitoring with reduced... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for system monitoring with reduced..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for system monitoring with reduced... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3776816