Semiconductor memory device having a multiple tunnel...

Details Semiconductor memory device having a multiple tunnel... Semiconductor memory device having a multiple tunnel...

2006-02-14

2006-02-14

Tran, Mai-Huong (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C257S020000, C257S023000, C257S024000, C257S028000, C257S331000, C257S903000, C257S904000

Reexamination Certificate

active

06998306

ABSTRACT:
The present invention discloses a semiconductor memory device having a multiple tunnel junction pattern and a method of forming the same. The semiconductor memory device includes a unit cell composed of planar transistor and vertical transistors. The planar transistor includes first and second conductive regions formed at predetermined regions of a semiconductor substrate and a storage node stacked on a channel region therebetween. The vertical transistor includes a storage node, a multiple tunnel junction pattern stacked thereon, a data line stacked thereon, and a word line for covering both sidewalls of the storage node and the multiple tunnel junction pattern. Width of the multiple tunnel junction pattern is narrower than the storage node and data lines. Semiconductor layers and tunnel oxide layers are alternately and repeatedly stacked and anisotropically etched to form the multiple tunnel junction pattern of narrow width while forming the data line and the storage node.

REFERENCES:
patent: 5952692 (1999-09-01), Nakazato et al.
patent: 6072718 (2000-06-01), Abraham et al.
patent: 6528896 (2003-03-01), Song et al.

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