Method and apparatus for deriving a bounded set of path...

Details Method and apparatus for deriving a bounded set of path... Method and apparatus for deriving a bounded set of path...

2006-05-02

2006-05-02

DeCady, Albert (Department: 2138)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S724000, C714S025000, C714S037000, C716S030000

Reexamination Certificate

active

07039845

ABSTRACT:
A method and apparatus for generating test patterns used to test an integrated circuit (IC). The apparatus comprises first logic for determining a subset of transition fault sites on an IC to be tested, second logic that identifies a longest sensitizable path through each transition fault site of the subset of transition fault sites, and third logic that generates a bounded set of test patterns that test the identified longest sensitizable paths through each transition fault site of the subset of transition fault sites. The present invention combines various aspects of transition fault modeling and path delay fault modeling to enable global delay testing of an IC within reasonable amount of time.

REFERENCES:
patent: 5600787 (1997-02-01), Underwood et al.
patent: 6018813 (2000-01-01), Chakradhar et al.
patent: 6453437 (2002-09-01), Kapur et al.
patent: 2002/0112213 (2002-08-01), Abadir et al.
patent: 2003/0079189 (2003-04-01), Abadir et al.
patent: 2003/0115526 (2003-06-01), Fetherson
Majhi et al., “Delay Fault Models and Coverage”, Jan. 4-7, 1998, IEEE VLSI Design Proceedings 1998, pp. 364-369.
Sharma et al., “Bounding Circuit Delay by Testing a Very Small Subset of Paths”, Apr. 30-May 4, 2000, IEEE VLSI Test Symposium Proceedings 2000, pp. 333-341.
Tsukiyama et al., “Techniques to remove false paths in statistical static timing analysis”, □□ASIC, 2001. Proceedings. 4th International Conference on Oct. 23-25, 2001 □□pp.: 39-44.

Affiliated with

Also associated with

Rating

Method and apparatus for deriving a bounded set of path... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and apparatus for deriving a bounded set of path..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for deriving a bounded set of path... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3608549