Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2006-07-11
2006-07-11
Ton, David (Department: 2138)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S729000
Reexamination Certificate
active
07076708
ABSTRACT:
A method of accessing an embedded microcontroller, by programmably selecting pins of the microcontroller for use as test lines, receiving a scan command at an input test line pin, emulating a virtual scan path through a logical block of the microcontroller, and transmitting scan results to an output test line pin. The microcontroller can provide such emulation of scan testing in compliance with the JTAG standard for a test access port and boundary-scan architecture. The test line pins are interconnected with a test bus structure to form a scan ring with other components of a data processing system, such as a microprocessor. The emulation can be used to change a functional mode of the microcontroller, or gather diagnostic information after a system error. The microcontroller assigns a high-priority internal interrupt routine to service test line pin activity. The virtual scan path need not include all internal microcontroller resources, and the scan path can be programmably varied by the application designer.
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Faust Robert Allan
Upton John Daniel
McBurney John
Musgrove Jack
Ton David
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