Method for simultaneous degas and baking in copper damascene...

Details Method for simultaneous degas and baking in copper damascene... Method for simultaneous degas and baking in copper damascene...

2006-04-18

2006-04-18

Norton, Nadine G. (Department: 1765)

Semiconductor device manufacturing: process

Chemical etching

Combined with coating step

C438S710000, C438S712000, C438S715000

Reexamination Certificate

active

07030023

ABSTRACT:
A method for forming a copper damascene feature including providing a semiconductor process wafer including at least one via opening formed to extend through a thickness of at least one dielectric insulating layer and an overlying trench line opening encompassing the at least one via opening to form a dual damascene opening; etching through an etch stop layer at the at least one via opening bottom portion to expose an underlying copper area; carrying out a sub-atmospheric DEGAS process with simultaneous heating of the process wafer in a hydrogen containing ambient; carrying out an in-situ sputter-clean process; and, forming a barrier layer in-situ to line the dual damascene opening.

REFERENCES:
patent: 6554914 (2003-04-01), Rozbicki et al.
patent: 6767788 (2004-07-01), Kim
patent: 2004/0023485 (2004-02-01), Pan et al.
patent: 2004/0127002 (2004-07-01), Kim

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