Multi-port scan chain register apparatus and method

Details Multi-port scan chain register apparatus and method Multi-port scan chain register apparatus and method

2005-01-25

2005-01-25

Ton, David (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S727000

Reexamination Certificate

active

06848067

ABSTRACT:
A memory apparatus, which may be of resistive cross point memory (RXPtM) cell type (one example of which is a magnetic random access memory (MRAM)) includes multiple serial data paths which are merged and may exchange data as needed by the data input/output (I/O) circuits connected to a serial I/O port. A plurality of scan path registers are connected by an array of static random access memory (SRAM) memory units of plural memory cells. The scan paths and SRAM memory units perform a parallel transfer of data from scan path registers to and from temporary registers of the SRAM memory units in order to effect parallel data exchange between the multiple scan path registers.

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