Process integration for integrated circuits

Details Process integration for integrated circuits Process integration for integrated circuits

2005-05-17

2005-05-17

Deo, Duy-Vu N. (Department: 1765)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S691000, C438S745000, C257S506000, C257S510000

Reexamination Certificate

active

06893911

ABSTRACT:
A process for fabricating integrated circuits is disclosed. In particular, the process includes rounding corners of the active regions. In one embodiment, a substrate prepared with a support region having an active area between first and second trench isolations. The top surfaces of the trench isolations extend above the surface of the substrate. First and second etch stop layers are deposited on the substrate, lining the substrate surface and trench isolations without filling the gap. The etch stop layers can be etched selective to each other and layers beneath and or above. The second etch stop layer includes horizontal and vertical portions. An etch selectively removes the vertical portions of the etch stop layer. An isotropic etch is then performed, removing exposed portions of the first etch stop layer. The second etch stop layer acts as an etch mask. The etch also creates an undercut beneath the second etch stop layer, exposing edge portions of the active area. The second etch stop layer is removed, following by oxidizing the edge portions of the active area unprotected by the first etch stop layer.

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Weis, et al., “A Highly Cost Efficient 8F2DRAM Cell with a Double Gate Vertical Transistor Device for 100 nm and Beyond,” International Electron Device Meeting IEDM, Washington (2001).

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